Document
PRELIMINARY
W147G
Frequency Generator for Integrated Core Logic
Features
• Maximized EMI suppression using Cypress’s Spread Spectrum Technology • Low jitter and tightly controlled clock skew • Highly integrated device providing clocks required for CPU, core logic, and SDRAM • Three copies of CPU clock at 66/100 MHz • Nine copies of 100-MHz SDRAM clocks • Eight copies of PCI clock • Two copies of synchronous APIC clock • Two copies of 48-MHz clock (non-spread spectrum) optimized for USB reference input and video dot clock • Two copies of 66-MHz fixed clock • One copy of 14.31818-MHz reference clock • Power-down control • I2C interface for turning off unused clocks
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: .............. 250 ps APIC, 48MHz, 3V66, PCI Outputs Cycle-to-Cycle Jitter: ...................................................500 ps APIC, 48MHz, SDRAM Output Skew: ......................... 250 ps CPU, 3V66 Output Skew: ............................................175 ps PCI Output Skew: ........................................................500 ps CPU to SDRAM Skew (@ 100 MHz):................. 4.5 to 5.5 ns CPU to 3V66 Skew (@ 66 MHz): ....................... 7.0 to 8.0 ns 3V66 to PCI Skew (3V66 lead):.......................... 1.5 to 3.5 ns PCI to APIC Skew: .....................................................±0.5 ns Table 1. Pin Selectable Functions SEL1 0 0 1 1 SEL0 0 1 0 1 Function Three-state Test 66-MHz CPU 100-MHz CPU
Block Diagram
VDDQ3
Pin Configuration
REF/APICDIV VDDQ3 X1 X2 GND GND 3V66_0 3V66_1 VDDQ3 VDDQ3 PCI0_ICH PCI1 PCI2 GND PCI3 PCI4 GND PCI5 PCI6 PCI7 VDDQ3 VDD3 GND GND USB DOT VDDQ3 SEL0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND APIC0 APIC1 VDDQ2 CPU0 VDDQ2 CPU1 CPU2_ITP GND GND SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDQ3 SDRAM6 SDRAM7 GND DCLK VDDQ3 PWRDWN# SCLK SDATA SEL1
X1 X2
XTAL OSC
PLL REF FREQ
REF/APICDIV
VDDQ2
SDATA SCLK
I2C Logic
Divider, Delay, and Phase Control Logic
2
CPU0:1 CPU2_ITP APIC0:1 VDDQ3
W147G
2
SEL0:1
PLL 1
2
3V66_0:1
PCI0_ICH
7
PCI1:7
DCLK PWRDWN#
8
SDRAM0:7
PLL2
VDDQ3 USB DOT
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600 October 13, 1999, rev. **
PRELIMINARY
Pin Definitions
Pin Name REF/APICDIV Pin No. 1 Pin Type I/O Pin Description
W147G
Reference Clock: 3.3V 14.318-MHz clock output. This pin doubles as the select strap for APIC clock frequency. If strapped LOW during power up, APIC clock runs at half PCI clock speed. Otherwise, APIC clocks run at PCI clock speed. Crystal Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection as an external reference frequency input. Crystal Output: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. PCI Clock 0 thro.