W147

PRELIMINARY W147G Frequency Generator for Integrated Core Logic Features Maximized EMI suppression using Cypress’s Spread Spectrum Technology Low jitter and tightly controlled clock skew Highly integrated device providing clocks required for CPU, core logic, and SDRAM Three copies of CPU clock at 66/100 MHz Nine copies of 100-MHz SDRAM clocks Eight copies of PCI clock Two copies of synchronous APIC clock Two copies of 48-MHz clock (non-spread spectrum) optimized for USB reference input and video dot clock Two copies of 66-MHz fixed clock One copy of 14.31818-MHz reference clock Power-down control I2C interface for turning off unused clocks Key Specifications CPU, SDRAM Outputs Cycle-to-Cycle Jitter: .............. 250 ps APIC, 48MHz, 3V66, PCI Outputs Cycle-to-Cycle Jitter: ...................................................500 ps APIC, 48MHz, SDRAM Output Skew: ......................... 250 ps CPU, 3V66 Output Skew: ............................................175 ps PCI Output Skew: ........................................................500 ps CPU to SDRAM Skew (@ 100 MHz):................. 4.5 to 5.5 ns CPU to 3V66 Skew (@ 66 MHz): ....................... 7.0 to 8.0 ns 3V66 to PCI Skew (3V66 lead):.......................... 1.5 to 3.5 ns PCI to APIC Skew: .....................................................±0.5 ns Table 1. Pin Selectable Functions SEL1 0 0 1 1 SEL0 0 1 0 1 Function Three-state Test 66-MHz CPU 100-MHz CPU Block Diagram VDDQ3 Pi...