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W137 Dataheets PDF



Part Number W137
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description Bx Notebook System Frequency Synthesizer
Datasheet W137 DatasheetW137 Datasheet (PDF)

W137 Bx Notebook System Frequency Synthesizer Features • Maximized EMI suppression using Cypress’s Spread Spectrum Technology • Two copies of CPU output • Six copies of PCI output (Synchronous w/CPU output) • One 48-MHz output for USB support • One selectable 24-/48-MHz output • Two Buffered copies of 14.318-MHz input reference signal • Supports 100-MHz or 66-MHz CPU operation • Power management control input pins • Available in 28-pin SSOP (209 mils) • SS function can be disabled • See W40S11-.

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W137 Bx Notebook System Frequency Synthesizer Features • Maximized EMI suppression using Cypress’s Spread Spectrum Technology • Two copies of CPU output • Six copies of PCI output (Synchronous w/CPU output) • One 48-MHz output for USB support • One selectable 24-/48-MHz output • Two Buffered copies of 14.318-MHz input reference signal • Supports 100-MHz or 66-MHz CPU operation • Power management control input pins • Available in 28-pin SSOP (209 mils) • SS function can be disabled • See W40S11-02 for 2 SDRAM DIMM support PCI_F, PCI1:5 Output to Output Skew:........................ 500 ps PCI_F, PCI1:5 Cycle to Cycle Jitter: ............................ 250 ps CPU to PCI Output Skew: ............... 1.5–4.0 ns (CPU Leads) Output Duty Cycle: .................................................... 45/55% PCI_F, PCI Edge Rate: .............................................. >1 V/ns CPU_STOP#, OE, SPREAD#, SEL48#, PCI_STOP#, PWR_DWN# all have a 250-kΩ pull-up resistor. Table 1. Pin Selectable Frequency SEL100/66# 0/1 0 1 OE 0 1 1 CPU HI-Z 66.6 MHz 100 MHz PCI HI-Z 33.3 33.3 Spread% Don’t Care See Table 2 See Table 2 Key Specifications Supply Voltages: ....................................... VDDQ3 = 3.3V±5% VDDQ2 = 2.5V±5% CPU0:1 Output to Output Skew: ................................ 175 ps CPU0:1 Cycle to Cycle Jitter: ..................................... 200 ps Table 2. Spread Spectrum Feature SPREAD# 0 1 Spread Profile –0.5% (down spread) 0% (spread disabled) Block Diagram X1 X2 CPU_STOP# Pin Configuration 2 REF0:1 XTAL OSC STOP Clock Logic 4 CPU0:3 2 SPREAD# SEL0 SEL1 SEL133/100# ÷2 CPUdiv2_0:1 PLL 1 ÷2/÷1.5 STOP Clock Logic 4 3V66_0:3 GND X1 X2 PCI_F PCI1 PCI2 GND VDDQ3 PCI3 PCI4 PCI5 VDDQ3 48MHz 24/48MHz/OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDDQ3 REF0/SEL48# REF1/SPREAD# VDDQ2 CPU0 CPU1 GND GND PCI_STOP# VDDQ3 CPU_STOP# PWR_DWN# SEL100/66# GND 1 PCI_F STOP Clock Logic 7 PCI1:7 PWRDWN# PCI_STOP# ÷2 Power Down Logic 3 ÷2 IOAPIC0:2 Three-state Logic PLL2 1 48MHz Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 October 12, 1999, rev. ** W137 Pin Definitions Pin Name CPU0:1 Pin No. 24, 23 Pin Type O Pin Description CPU Clock Outputs 0 and 1: These two CPU clock outputs are controlled by the CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ2. Frequency is selected per Table 1. PCI Bus Clock Outputs 1 through 5: These five PCI clock outputs are controlled by the PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to VDDQ3. Frequency is selected per Table 1. Fixed PCI Clock Output: Unlike PCI1:5 outputs, this output is not controlled by the PCI_STOP# control pin; it cannot be forced LOW by PCI_STOP#. Output voltage swing is controlled by voltage applied to VDDQ3. Frequency is selected per Table 1. CPU_STOP# Input: When brought LOW, clock outputs CPU0:1 are stopped LOW after completing a full clock cycle (2–3 CPU clock latency). When brought HIGH, clock outputs CPU0:1 start with a full clock cycle (2–3 CPU clock latency). PCI_STOP# Input: The PCI_STOP# input enables the PCI1:5 outputs when HIGH and causes them to remain at logic 0 when LOW. The PCI_STOP# signal is latched on the rising edge of PCI_F. Its effect takes place on the next PCI_F clock cycle. I/O Dual-Function REF0 and SEL48# Pin: Upon power-up, the state of SEL48# is latched. The state is set by either a 10K resistor to GND or to VDD. A 10K resistor to GND causes pin 14 to provide a 48-MHz clock. If the pin is strapped to VDD, pin 14 will provide a 24-MHz clock. After 2 ms, the pin becomes a high-drive output that produces a copy of 14.318 MHz. I/O Dual-Function REF1 and SPREAD# Pin: Upon power-up, the state of SPREAD# is latched. The state is set by either a 10K resistor to GND or to VDD. A 10K resistor to GND enables Spread Spectrum function. If the pin is strapped to VDD, Spread Spectrum is disabled. After 2 ms, the pin becomes a high-drive output that produces a copy of 14.318 MHz. I/O Dual-Function 24-MHz or 48-MHz Output and Output Enable Input: Upon power-up, the state of pin 14 is latched. The state is set by either a 10K resistor to GND or to VDD. A 10K resistor to GND latches OE LOW, and all outputs are threestated. If the pin is strapped to VDD, OE is latched HIGH and all outputs are active. After 2 ms, the pin becomes an output whose frequency is set by the state of pin 27 on power-up. 48-MHz Output: Fixed 48-MHz USB output. Output voltage swing is controlled by voltage applied to VDDQ3. Frequency Selection Input: Select power-up default CPU clock frequency as shown in Table 1. Crystal Connection or External Reference Frequency Input: This pin can either be used as a connection to a crystal or to a reference signal. Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Power Down .


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