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VT98501S1X Dataheets PDF



Part Number VT98501S1X
Manufacturers Vaishali Semiconductor
Logo Vaishali Semiconductor
Description 3.3V Low Phase Noise Clock Multiplier
Datasheet VT98501S1X DatasheetVT98501S1X Datasheet (PDF)

Advance Information Advance Information VT98501 VT98501 Low Phase Noise Clock Multiplier 3.3V Low Phase Noise Clock Multiplier Applications •= Oscillator Replacement •= LCD monitor clock source General Description The VT98501 is a 3.3V CMOS, clock multiplier integrated circuit. The device provides an excellent quality high frequency output clock from a lower frequency crystal or clock input. Tri-level selection inputs S0 and S1 are used to select any one of nine multipliers, stored in the on-b.

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Advance Information Advance Information VT98501 VT98501 Low Phase Noise Clock Multiplier 3.3V Low Phase Noise Clock Multiplier Applications •= Oscillator Replacement •= LCD monitor clock source General Description The VT98501 is a 3.3V CMOS, clock multiplier integrated circuit. The device provides an excellent quality high frequency output clock from a lower frequency crystal or clock input. Tri-level selection inputs S0 and S1 are used to select any one of nine multipliers, stored in the on-board ROM, and apply it to the input to produce the desired output. The resulting output includes many commonly used frequencies up to 160 MHz. Phase Locked Loop (PLL) technology allows the device to use an input signal from an inexpensive crystal. When Output Enable (OE) is low, the clock output is in high impedance state. The VT98501, when used with an inexpensive crystal, provides a cost-effective clock source for most electronic systems. Features •= •= •= •= •= •= Low phase noise Zero ppm multiplication error Input clock frequency 2 - 50 MHz. Input crystal frequency 5 – 27 MHz Output clock frequencies up to 160 MHz. 5V tolerant inputs and output •= •= •= •= •= Exceptionally low jitter: 25 ps one sigma Fully Compatible with all popular CPUs Duty Cycle of 45/55 up to 160 MHz. 25mA drive capability at TTL levels High-Z output for board level testing Figure 1. Functional Block Diagram Figure 2. Pin Assignment VDD GND 8-pin SOIC S0 S1 Clock or Xtal X1/ICLK input PLL Clock Multiplier & ROM Xtal. Osc. Output Buffer CLK X1/ICLK VDD GND S1 1 2 3 4 8 7 6 5 X2 OE S0 CLK X2 Optional caps Output Enable 2001-03-05 Vaishali Semiconductor Page 1 1300 White Oaks Road, Ste. 200 Campbell CA 95008 Ph. 408.377.6060 MDST-0009-00 Fax 408.377.6063 VT98501 Advance Information Table 1. Clock Output Table S1 0 0 0 M M M 1 1 1 S0 0 M 1 0 M 1 0 M 1 CLK 4 x input 5.3125 x input 5 x input 6.25 x input 2 x input 3.125 x input 6 x input 3 x input 8 x input Minimum Input See table 7 20 MHz See table 7 4 MHz See table 7 8 MHz See table 7 See table 7 See table 7 0 = Connect to ground. 1 = Connect directly to VDD M = Leave unconnected (floating) Table 2. Examples of Common Output Frequencies. Output Input Selection (S1,S0) Output Input Selection (S1,S0) Output Input Selection (S1,S0) 20 10 M,M 50 16.66 1,M 83.33 16.66 0,1 24 12 M,M 60 10 1,0 90 15 1,0 30 10 1,M 62.5 20 M,1 100 20 0,1 32 16 M,M 64 16 0,0 33.33 16.66 M,M 66.66 16.66 0,0 120 15 1,1 37.5 12 M,1 72 12 1,0 125 20 M,0 40 10 0,0 75 12 M,0 48 12 0,0 80 10 1,1 155.52 19.44 1,1 106.25 20 0,M Table 3. Pin Description No. 1 2 3 4 5 6 7 8 Name X1/ICLK VDD GND S1 CLK S0 OE X2 Type I P P TI O TI I O Description Xtal connection or clock input. Connect to +3.3V Connect to ground. Select 1 for output clock. Connect to ground or VDD or float Clock output per table 2. Select 0 for output clock. Connect to ground or VDD or float. Output Enable. Tri- states CLK output when low. Xtal connection. Leave unconnected for clock input. Legend: I = Input TI = Tri-level Input O = Output P = Power supply connection 2001-03-05 Vaishali Semiconductor Page 2 1300 White Oaks Road, Ste 200 Campbell CA 95008 Ph. 408.377.6060 MDST-0009-00 Fax 408.377.6063 VT98501 Advance Information Table 4. Absolute Maximum Ratings Parameter Supply voltage, VDD Inputs and Clock Outputs Soldering Temperature Storage temperature Conditions Referenced to GND Referenced to GND Max of 10 seconds Min -0.5 Typ Max 4.6 4.6 260 Units V V °C °C -65 150 Table 5. Operating Conditions Parameter Ambient Operating Temperature Operating Voltage, VDD Input High Voltage, VIH, X1 pin only Input Low Voltage, VIL, X1 pin only Input High Voltage, VIH, OE pin Input Low Voltage, VIL, OE pin Input High Voltage, VIH, trinary inputs Input Low Voltage, VIL, trinary inputs VDD-0.5 0.5 2 0.8 Min 0 3 2.5 Typ Max 70 3.6 Units °C V V 1.65 1.65 0.5 V V V V V DC Characteristics Table 6. DC Characteristics VDD = 3V to 3.6V Parameter Output High Voltage, VOH Output Low Voltage, VOL Operating Supply Current, IDD (20 MHz Xtal) Short Circuit Current Input Capacitance Frequency synthesis error Condition IOH=-25mA IOL=25mA No Load, 100MHz CLK output S0, S1, OE Min 2.4 Typ Max 0.4 Units V V mA mA pF 25 ±100 4 0 ppm 2001-03-05 Vaishali Semiconductor Page 3 1300 White Oaks Road, Ste 200 Campbell CA 95008 Ph. 408.377.6060 MDST-0009-00 Fax 408.377.6063 VT98501 Advance Information AC Characteristics Table 7. AC Characteristics VDD = 3V to 3.6V over the operating temperature range Symbol fosc fin fout tr tf tod Parameter Input Crystal Frequency Input clock frequency Output Frequency, Output Clock Rise Time Output Clock Fall Time Output Clock Duty Cycle PLL Bandwidth Condition Min 5 2 14 Typ Max 27 50 160 Units MHz MHz MHz ns ns 0.8 to 2.0V 2.0 to 0.8V 1.5 V, up to 160 MHz 45 10 1 1 49 to 51 55 % kHz TPZH, TPZL TPHZ, TPLZ tjit (abs) tjit (sigma) Output Enable Time, OE high to output on Output Disable time, OE low t.


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