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UPD16772 Dataheets PDF



Part Number UPD16772
Manufacturers NEC
Logo NEC
Description 480-OUTPUT TFT-LCD SOURCE DRIVER
Datasheet UPD16772 DatasheetUPD16772 Datasheet (PDF)

DATA SHEET MOS INTEGRATED CIRCUIT µ PD16772 480-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64-GRAY SCALES) DESCRIPTION The µ PD16772 is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output dynamic range is a.

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DATA SHEET MOS INTEGRATED CIRCUIT µ PD16772 480-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64-GRAY SCALES) DESCRIPTION The µ PD16772 is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output dynamic range is as large as VSS2 + 0.1 V to VDD2 – 0.1 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a clock frequency of 45 MHz when driving at 2.3 V, this driver is applicable to UXGA-standard TFT-LCD panels. FEATURES • CMOS level input (2.3 to 3.6 V) • 480 outputs • Input of 6 bits (gradation data) by 6 dots • Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (RDAC) • Output dynamic range : VSS2 + 0.1 V to VDD2 – 0.1 V • High-speed data transfer : fCLK = 45 MHz (internal data transfer speed when operating at VDD1 = 2.3 V) • Apply for dot-line inversion, n-line inversion and column line inversion • Output voltage polarity inversion function (POL) • Display data inversion function (POL21/22) • Current consumption reduction function (LPC, Bcont) • Logic power supply voltage (VDD1) : 2.3 to 3.6 V • Driver power supply voltage (VDD2) : 8.5 V ± 0.5 V ORDERING INFORMATION Part Number Package TCP (TAB package) µ PD16772N-xxx Remark The TCP’s external shape is customized. To order the required shape, so please contact one of our sales representatives. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14416EJ1V0DS00 (1st edition) Date Published August 2000 NS CP (K) Printed in Japan The mark • shows major revised points. © 1999, 2000 µPD16772 1. BLOCK DIAGRAM STHR R,/L CLK STB C1 C2 STHL VDD1 VSS1 C79 C80 80-bit bidirectional shift register D00 - D05 D10 - D15 D20 - D25 D30 - D35 D40 - D45 D50 - D55 POL21/22 Data register POL Latch VDD2 Level shifter VSS2 V0 - V9 D/A converter LPC Bcont Voltage follower output S1 S2 S3 S480 Remark /xxx indicates active low signal. 2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER S1 S2 S479 S480 V0 V4 V5 V9 Multiplexer 5 6-bit D/A converter 5 POL 2 Data Sheet S14416EJ1V0DS00 µPD16772 3. PIN CONFIGURATION (µPD16772N-xxx: TCP (TAB package)) STHL D55 D54 D53 D52 D51 D50 D45 D44 D43 D42 D41 D40 D35 D34 D33 D32 D31 D30 VDD1 R,/L V9 V8 V7 V6 V5 VDD2 VSS2 Bcont V4 V3 V2 V1 V0 VSS1 LPC CLK STB POL POL21 POL22 D25 D24 D23 D22 D21 D20 D15 D14 D13 D12 D11 D10 D05 D04 D03 D02 D01 D00 STHR S480 S479 S478 S477 Copper Foil Surface S4 S3 S2 S1 Remark This figure does not specify the TCP package. Data Sheet S14416EJ1V0DS00 3 µPD16772 4. PIN FUNCTIONS Pin Symbol S1 to S480 D00 to D05 D10 to D15 D20 to D25 D30 to D35 D40 to D45 D50 to D55 R,/L Shift direction control These refer to the start pulse I/O pins when driver ICs are connected in cascade. The shift input directions of the shift registers are as follows. R,/L = H: STHR input, S1 → S480, STHL output R,/L = L: STHL input, S480 → S1, STHR output Right shift start pulse These refer to the start pulse I/O pins when driver ICs are connected in cascade. Fetching of display data starts when H is read at the rising edge of CLK. input/output Left shift start pulse R,/L = H (right shift): STHR input, STHL output R,/L = L (left shift): STHL input, STHR output input/output The start pulse width (H level) for next-level drivers is 1CLK. Shift clock input Refers to the shift register’s shift clock input. The display data is incorporated into the data register at the rising edge. At the rising edge of the 80th clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. If 82 clock pulses are input after input of the start pulse, input of display data is halted automatically. The contents of the shift register are cleared at the STB’s rising edge. The contents of the data register are transferred to the latch circuit at the rising edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure input of one pulse per horizontal period. POL = L: The S2n–1 output uses V0 to V4 as the reference supply. The S2n output uses V5 to V9 as the reference supply. POL = H: The S2n–1 outp.


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