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BU2385KN Dataheets PDF



Part Number BU2385KN
Manufacturers Rohm
Logo Rohm
Description Clock generator for digital still camera
Datasheet BU2385KN DatasheetBU2385KN Datasheet (PDF)

Multimedia ICs BU2385KN Clock generator for digital still camera BU2385KN BU2385KN is a clock generator IC that can generate multiple frequencies (clocks) from one oscillator. Excellent jitter characteristic is achieved through the built-in high-performance 3-channel PLL. High-quality sound and image equivalent to the oscillating module are the result of this feature. Clocks can be easily changed for other applications. The internal dividing control allows the frequency to be switched outsid.

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Multimedia ICs BU2385KN Clock generator for digital still camera BU2385KN BU2385KN is a clock generator IC that can generate multiple frequencies (clocks) from one oscillator. Excellent jitter characteristic is achieved through the built-in high-performance 3-channel PLL. High-quality sound and image equivalent to the oscillating module are the result of this feature. Clocks can be easily changed for other applications. The internal dividing control allows the frequency to be switched outside. zApplications Digital still camera zFeatures 1) Multiple frequency clock signals can be generated by the built-in 3-channel PLL through connecting crystal oscillator. 2) QFN20V package 3) 3.3V single power supply 4) For crystal 14.318182MHz • 28.636363MHz 5) No need additional components. (BU2385KN have PLL loop filter in side). zExternal dimensions (Unit : mm) 1.1+− 0.15 0.6+−00..135 0.5−0+.04.2 0.20−+0.1 0.5 0.20+−0.05 0.05 M 3−0.35+−0.25 44..02++−−00..11 0.2+−0.05 44..20++−−00..11 15 11 16 10 20 6 15 12 12 0.05 QFN20V 0.01+−00..00307 0.6+−0.1 0.8+−0.15 zAbsolute maximum ratings (Ta=25°C) Parameter Symbol Limits Applied voltage VDD −0.5 to +7.0 Input voltage VIN −0.3 to VDD+0.3 Storage temperature range Tstg −30 to +125 Power dissipation Pd 530 ∗ An operation is not guaranteed. ∗ In case it is used at Ta=25 C or more, 5.3mW is reduced at every 1 C. ∗ Radiation resistance design is not used. ∗ Power dissipation is measured when BU2385KN is placed in the board. Unit V V C mW zRecommended operating conditions (Ta=25°C) Parameter Supply voltage Input H voltage range Input L voltage range Operation temperature range Output maximum load Symbol VDD VIH VIL Topr CL Min. 3.0 0.8VDD 0.0 −5 − Typ. − − − − − Max. 3.6 VDD 0.2VDD +70 15 Unit V V V C pF 1/4 Multimedia ICs zBlock diagram BU2385KN TEST2 REF_CLK VDD2 VSS2 CLK2OUT AVDD 1 AVDD 2 AVSS 3 XIN 4 XOUT 5 20 19 18 17 16 Back View 15 VDD1 14 VDD1 13 VSS1 12 CKL2ON 11 CLK1_OUT 6 7 8 9 10 TEST1 XTAL_SEL FS3 FS2 FS1 zExplanation for terminal function PIN No. 1 2 3 4 5 PIN NAME AVDD AVDD AVSS XIN XOUT 6 TEST 1 7 XTAL_SEL 8 FS3 9 FS2 10 FS1 11 CLK1OUT 12 CLK2ON 13 VSS 1 14 VDD 1 15 VDD 1 16 CLK2OUT 17 VSS 2 18 VDD 2 19 REF_CLK 20 TEST2 Analog VDD Analog VDD Function Analog GND Standard crystal input Standard crystal output Input for test mode (normally open) Crystal select H : 28.636363MHz with pull−down with pull up L : 14.318182MHz CLK1,2 output select CLK1,2 output select REFCLK output select with pull up with pull up with pull up 71.877274M / 90.314686M / 96.016044M / 114.54546M clock output CLK2 output control with pull up H : enable L : disable GND for CLK 1, 2 clock output and Logic circuit VDD for CLK 1, 2,clock output and Logic circuit VDD for CLK 1, 2,clock output and Logic circuit 96.016044M / 48.008022M clock output REF_CLK GND REF_CLK VDD 14.318182M / 17.734450M clock output Input for test mode (normally open) with pull−down 2/4 Multimedia ICs zPIN Input / Output equivalent circuit PIN No. Input PIN 7, 8, 9, 10, 12 with pull−up (6 : TEST1, 20 : TEST2 with pull down) Output PIN 11, 16, 19 Equival circuit BU2385KN To inside IC From inside IC Crystal PIN 4, 5 XTALIN XTALOUT To inside IC 3/4 Multimedia ICs BU2385KN zElectrical characteristics (Unless otherwise noted, Ta=25°C, VCC=3.3V) While crystal shows 28.636363MHz, XTAL_SEL=H, in case of 14.31818MHz, TXAL_SEL=L Parameter Symbol Min. Typ. Max. Unit Power supply current IDD - 40 50 mA No load Conditions output frequency CLK1 FS2:H FS3:H Fclk1-1 − 96.016044 − FS2:H FS3:L Fclk1-2 − 71.877274 − FS2:L FS3:L Fclk1-3 − 114.54546 − FS2:L FS3:H Fclk1-4 − 90.314686 − CLK2 FS2:L FS3:L Fclk2-1 − 96.016044 − FS2,3:HL LH HH Fclk2-2 − 48.008022 − REFCLK FS1:H Fref1-1 − 14.318182 − FS1:L Fref1-2 − 17.734450 − Duty1 at under 100MHz Duty1 45 50 55 MHz MHz MHz MHz MHz MHz % Xtal * (228/17)/2 Xtal * (251/25)/2 Xtal * (224/14)/2 Xtal * (164/13)/2 Xtal * (228/17)/2 Xtal * (228/17)/4 Crystal direct output Xtal * (706/57)/10 Measured at 1/2VDD Duty2 at upper 100MHz Duty2 − 50 − % Measured at 1/2VDD Rise time Tr − 2.5 − nsec Time between 0.2VDD and 0.8VDD Fall time Tf − 2.5 − nsec Time between 0.2VDD and 0.8VDD Period Jitter 1σ P-J1σ − 30 − psec ∗1 Period Jitter MIN-MAX P-J MINMAX − 180 − psec ∗2 Output Lock time Tlock − − 1 msec ∗3 Note) When input frequency is 14.31818MHz, output frequency is above rated value. ∗1 Period Jitter 1σ : This value is the standard deviation of an output period when using Time Interval Analyzer with 10,000 sampling. ∗2 Period Jitter MIN-MAX : This value is the max range of an output period when using Time Interval Analyzer with 10,000 sampling. ∗3 Output Lock time : Time between voltage supply leads to 3.0V and output clock gets stable. zApplication circuit 14.318182MHz 17.734450MHz 48.008022MHz 96.016044MHz TEST2 REF_CLK VDD2 VSS2 CLK2OUT AVDD AVDD AVSS XIN XOUT .


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