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PCA8550 Dataheets PDF



Part Number PCA8550
Manufacturers NXP
Logo NXP
Description 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM
Datasheet PCA8550 DatasheetPCA8550 Datasheet (PDF)

INTEGRATED CIRCUITS PCA8550 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM Product specification 1998 Sep 29 Philips Semiconductors Philips Semiconductors Product specification 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM PCA8550 FEATURES •4-bit 2-to-1 multiplexer, 1-bit latch •5-bit internal non-volatile register •Override input forces all outputs to logic 0 •Internal non-volatile register write/readable via I2C bus •Write-protect pin enables/disables I2C writes to register •2.5V .

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INTEGRATED CIRCUITS PCA8550 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM Product specification 1998 Sep 29 Philips Semiconductors Philips Semiconductors Product specification 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM PCA8550 FEATURES •4-bit 2-to-1 multiplexer, 1-bit latch •5-bit internal non-volatile register •Override input forces all outputs to logic 0 •Internal non-volatile register write/readable via I2C bus •Write-protect pin enables/disables I2C writes to register •2.5V multiplexed outputs •3.3V non-multiplexed output (latched) •5V tolerant inputs •Useful for ’jumperless’ configuration of PC motherboards •Designed for use in Pentium Pro/Pentium II™ systems Pentium II is a registered trademark of Intel Corporation PIN CONFIGURATION 2 I C SCL 1 16 VCC 15 WP 14 NON_MUXED_OUT 13 MUX_SELECT 12 MUX_OUT A 11 MUX_OUT B 10 MUX_OUT C 9 MUX_OUT D I2C SDA 2 OVERRIDE# 3 MUX_IN A 4 MUX_IN B 5 MUX_IN C 6 MUX_IN D 7 GND 8 SW00216 DESCRIPTION The primary function of the 4-bit 2-to-1 I2C multiplexer is to select either a 4-bit input or data from a non-volatile register and drive this value onto the output pins. One additional non-multiplexed register output is also provided. The non-multiplexed output is latched to prevent output value changes during I2C writes to the non-volatile register. A write protect input is provided to enable/disable the ability to write to the non-volatile register. An ‘‘override” input feature forces all outputs to logic 0. ORDERING INFORMATION PACKAGES 16-Pin Plastic SO 16-Pin Plastic SSOP 16-Pin Plastic TSSOP TEMPERATURE RANGE 0°C to +70°C 0°C to +70°C 0°C to +70°C OUTSIDE NORTH AMERICA PCA8550D PCA8550DB PCA8550PW NORTH AMERICA PCA8550D PCA8550DB PCA8550PW DH DRAWING NUMBER SOT109-1 SOT338-1 SOT403-1 FUNCTIONAL DESCRIPTION When the MUX_SELECT signal is logic 0, the multiplexer will select the data from the non-volatile register to drive on the MUX_OUT pins. When the MUX_SELECT signal is logic 1, the multiplexer will select the MUX_IN lines to drive on the MUX_OUT pins. The MUX_SELECT signal is also used to latch the NON_MUXED_OUT signal which outputs data from the non-volatile register. The NON_MUXED_OUT signal latch is transparent when MUX_SELECT is in a logic 0 state, and will latch data when MUX_SELECT is in a logic 1 state. When the active-LOW OVERRIDE# signal is set to logic 0 and the MUX_SELECT signal is at a logic 0, all outputs will be driven to logic 0. This information is summarized in Table 1. The write protect (WP) input is used to control the ability to write the contents of the 5-bit non-volatile register. If the WP signal is logic 0, the I2C bus will be able to write the contents of the non-volatile register. If the WP signal is logic 1, data will not be allowed to be written into the non-volatile register. The factory default for the contents of the non-volatile register are all logic 0. These stored values can be read or written using the I2C bus (described in the next section). The OVERRIDE#, WP, MUX_IN, and MUX_SELECT signals have internal pullup resistors. See the DC and AC Characteristics for hysteresis and signal spike suppression figures. 1998 Sep 29 2 853-2015 20105 Philips Semiconductors Product specification 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM PCA8550 PIN DESCRIPTION PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 SYMBOL I2C SCL I2C SDA OVERRIDE# MUX_IN A MUX_IN B MUX_IN C MUX_IN D GND MUX_OUT D MUX_OUT C MUX_OUT B MUX_OUT A MUX_SELECT Selects MUX_IN inputs or register contents for MUX_OUT outputs TTL-level output from non-volatile memory Non-volatile register write-protect Positive voltage rail 2 5V multi 2.5V multiplexed lexed output out ut Common ground voltage rail External in inputs uts to multiplexer multi lexer FUNCTION I2C bus clock Bi-directional I2C bus data Forces all outputs to logic 0 FUNCTION TABLE Table 1. Function table OVERRIDE # 0 0 MUX_SELECT 0 1 MUX_OUT OUTPUTS All 0’s MUX_IN inputs From nonvolatile register MUX_IN inputs NON_MUXED_OUT OUTPUT All 0’s Latched NON_MUXED_OUT1 1 0 From non-volatile register From non-volatile register 1 1 NOTE 1. Latched NON_MIXED_OUT state will be the value present on the NON_MUXED_OUT output at the time of the MUX_SELECT input transitioned from a logic 0 to a logic 1 state. 14 15 16 I2C Interface NON_MUXED_OUT WP VCC Communicating with this device is initiated by sending a valid address on the I2C bus. The address format (see FIgure 1) is a fixed unique 7-bit value followed by a 1-bit read/write value which determines the direction of the data transfer. MSB LSB 1 0 0 1 1 1 0 R/W# SW00218 Figure 1. I2C Address Byte Following the address and acknowledge bit are 8 data bits which, depending on the read/write bit in the address, will read data from or write data to the non-volatile register. Data will be written to the register if the read/write bit is logic 0 and the WP input is logic 0. Data will be read from the register if the bit is logic 1. The thr.


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