LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
Description
(FOLSVH,, )DPLO\ 'DWD 6KHHW
/RZ 3RZHU )3*$ &RPELQLQJ 3HUIRUPDQFH 'HQVLW\ DQG (PEHGGHG 5$0
'HYLFH +LJKOLJKWV
)OH[LEOH 3URJUDPPDEOH /RJLF
0.18 µ, six layer metal CMOS process 1.8 V Vcc, 1.8/2.5/3.3 V drive capable I/O Up to 4,008 dedicated flip-flops Up to 55.3 K embedded RAM Bits Up to 313 I/O Up to 370 K system gates IEEE 1149.1 Boun...
