RDD104

UL ® LSI/CSI LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 LSI RDD 104 (631) 271-0400 FAX (631) 271-0405 January 2000 A3800 SELECTABLE 4 DECADE CMOS DIVIDER FEATURES: Selectable Divide by 10 or 100 or 1,000 or 10,000 Clock Input Shaping Network Accepts Fast or Slow Edge Inputs Active Oscillator Network for External Crystal Square Wave Output Output TTL Compatible at +4.5 Volt Operation High Noise Immunity Reset All Inputs Protected +4.5V to +15V Operation (VDD-VSS) Low Power Dissipaton RDD104 (DIP); RDD104-S (SOIC) - See Figure 1 PIN ASSIGNMENT - TOP VIEW DIVIDER SELECT-1 DIVIDER SELECT-2 1 8 V DD (+V) 2 RDD 104 7 OUTPUT V SS (-V) 3 6 CLOCK OUTPUT RESET 4 5 CLOCK INPUT DESCRIPTION OF OPERATION: The RDD104 is a monolithic CMOS four decade divider circuit that advances on each negative transition of the input clock pulse. When the reset input is high the circuit is cleared to zero. The clock input is applied to a three stage inverting amplifier network whose output is brought out so that an external crystal network can be used to form an oscillator circuit. If the clock output is not used,the amplifier acts as an input buffer. Two select inputs are provided which enables the circuit to divide by 10, 100, 1,000 or 10,000. FIGURE 1 MAXIMUM RATINGS: PARAMETER SYMBOL VALUE UNIT Storage Temperature Operating Temperature DC Supply Voltage Voltage at any input TSTG -65 to +150 TA -40 to +85 (VDD - VSS) +18 VIN VSS ...