Document
RLP1N06CLE
Data Sheet July 1999 File Number
2839.4
1A, 55V, 0.750 Ohm,Voltage Clamping, Current Limited, N-Channel Power MOSFET
The RLP1N06CLE is an intelligent monolithic power circuit which incorporates a lateral bipolar transistor, resistors, zener diodes, and a PowerMOS transistor. The current limiting of this device allows it to be used safely in circuits where it is anticipated that a shorted load condition may be encountered. The drain to source voltage clamping offers precision control of the circuit voltage when switching inductive loads. Logic level gates allow this device to be fully biased on with only 5V from gate to source. Input protection is provided for ESD up to 2kV. Formerly developmental type TA09880.
Features
• 1A, 55V • rDS(ON) = 0.750Ω • ILIMIT at 150oC = 1.1A to 1.5A Maximum • Built-in Voltage Clamp • Built-in Current Limiting • ESD Protected, 2kV Minimum • Controlled Switching Limits EMI and RFI • 175oC Rated Junction Temperature • Logic Level Gate • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards”
Ordering Information
PART NUMBER RLP1N06CLE PACKAGE TO-220AB BRAND L1N06CLE
Symbol
D
NOTE: When ordering, use the entire part number.
G
S
Packaging
JEDEC TO-220AB
SOURCE DRAIN GATE DRAIN (FLANGE)
6-428
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
RLP1N06CLE
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified RLP1N06CLE 55 55 2 Self Limited 5.5 36 0.24 -55 to 175 300 260 UNITS V V kV V W W/oC oC
oC oC
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS Drain to Gate Voltage (RGS = 20kΩ, Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Electrostatic Voltage at TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Gate to Source Voltage (Reverse Voltage Gate Bias Not Allowed) . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Power Dissipation Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage.