SM-BF50

Standard EEPROM ICs SLx 24C64 64 Kbit (8192 × 8 bit) Serial CMOS-EEPROM with I2C Synchronous 2-Wire Bus Data Sheet Preliminary 1998-07-27 SLx 24C64 Revision History: Previous Version: Page Page (in previous (in current Version) Version) 3 11, 12 21 24 24 I2C Bus Current Version: Preliminary 1998-07-27 05.98 Subjects (major changes since last revision) 3 11, 13 21 24 24 Text was changed to “Typical programming time 5 ms for up to 32 bytes”. The erase/write cycle is finished latest after 10 8 ms. The write or erase cycle is finished latest after 10 4 ms. The line “erase/write cycle” was removed. Chapter 8.4 “Erase and Write Characteristics” has been added. Purchase of Siemens I2C components conveys the license under the Philips I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. Edition Preliminary 1998-07-27 Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1998. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Gro...