SL74LS164

SL74LS164 8-Bit Serial-Input/Parallel-Output Shift Register This 8-bit shift register features gated serial inputs and an asynchronous reset. The gated serial inputs (A and B) permit complete control over incoming data as a low at either (or both) input(s) inhibits entry of the new data and resets the first flip flop to the low level at the next clock pulse. A high level input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the setup requirements will be entered clocking occurs or the low-to-high level transition of the clock input. All inputs are diodeclamped to minimize transmission-line effects. Gated (Enable/Disable) Serial Inputs Fully Buffered Clock and Serial Inputs Asynchronous Clear ORDERING INFORMATION SL74LS164N Plastic SL74LS164D SOIC TA =0° to 70°C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Reset L H H PIN 14 =VCC PIN 7 = GND H H Clock X A1 A2 X X X X H D D H L L Outputs QA QB ... QH L L ... L no change D QAn ... QGn D QAn ... QGn L QAn ... QGn D = data input X = don’t care QAn - QGn = data shifted from the previous stage on a rising edge at the clock input. SLS System Logic Semiconductor SL74LS164 MAXIMUM RATINGS * Symbol VCC VIN VOUT Tstg * Parameter Supply Voltage Input Voltage Output Voltage Storage Temperature Range Value 7.0 7.0 5.5 -65 to +150 Unit V V V °C Maximum Ratings are ...