Document
82C54
March 1997
CMOS Programmable Interval Timer
Description
The Intersil 82C54 is a high performance CMOS Programmable Interval Timer manufactured using an advanced 2 micron CMOS process. The 82C54 has three independently programmable and functional 16-bit counters, each capable of handling clock input frequencies of up to 8MHz (82C54) or 10MHz (82C54-10) or 12MHz (82C54-12). The high speed and industry standard configuration of the 82C54 make it compatible with the Intersil 80C86, 80C88, and 80C286 CMOS microprocessors along with many other industry standard processors. Six programmable timer modes allow the 82C54 to be used as an event counter, elapsed time indicator, programmable one-shot, and many other applications. Static CMOS circuit design insures low power operation. The Intersil advanced CMOS process results in a significant reduction in power with performance equal to or greater than existing equivalent products.
Features
• 8MHz to 12MHz Clock Input Frequency • Compatible with NMOS 8254 - Enhanced Version of NMOS 8253 • Three Independent 16-Bit Counters • Six Programmable Counter Modes • Status Read Back Command • Binary or BCD Counting • Fully TTL Compatible • Single 5V Power Supply • Low Power - ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10µA - ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA at 8MHz • Operating Temperature Ranges - C82C54 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC - I82C54 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC - M82C54 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Pinouts
82C54 (PDIP, CERDIP, SOIC) TOP VIEW
D7 1 D6 2 D5 3 D4 4 D3 5 D2 6 D1 7 D0 8 CLK 0 9 OUT 0 10 GATE 0 11 GND 12 24 VCC 23 WR 22 RD 21 CS 20 A1 19 A0 18 CLK 2 17 OUT 2 16 GATE 2 15 CLK 1 14 GATE 1 13 OUT 1
12 OUT 0 13 GATE 0 14 GND 15 NC 16 OUT 1 17 GATE 1 18 CLK 1 NC 11 19 GATE 2 D4 D3 D2 D1 D0 5 6 7 8 9 25 NC 24 CS 23 A1 22 A0 21 CLK2 20 OUT 2
82C54 (PLCC/CLCC) TOP VIEW
VCC WR 27 D5 D6 D7 NC RD 26
4
3
2
1
28
CLK 0 10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
File Number
2970.1
4-1
82C54 Ordering Information
PART NUMBERS 8MHz CP82C54 IP82C54 CS82C54 IS82C54 CD82C54 ID82C54 MD82C54/B MR82C54/B SMD # 8406501JA SMD# 84065013A CM82C54 10MHz CP82C54-10 IP82C54-10 CS82C54-10 IS82C54-10 CD82C54-10 ID82C54-10 MD82C54-10/B MR82C54-10/B CM82C54-10 12MHz CP82C54-12 IP82C54-12 CS82C54-12 IS82C54-12 CD82C54-12 ID82C54-12 MD82C54-12/B MR82C54-12/B 8406502JA 84065023A CM82C54-12 TEMPERATURE RANGE 0oC to +70oC -40oC to +85oC 0oC to +70oC -40oC to +85oC 0oC to +70oC -40oC to +85oC -55oC to +125oC -55oC to +125oC -55oC to +125oC -55oC to +125oC 0oC to +70oC PACKAGE 24 Lead PDIP 24 Lead PDIP 28 Lead PLCC 28 Lead PLCC 24 Lead CERDIP 24 Lead CERDIP 24 Lead CERDIP 28 Lead CLCC 24 Lead CERDIP 28 Lead CLCC 24 Lead SOIC PKG. NO. E24.6 E24.6 N28.45 N28.45 F24.6 F24.6 F24.6 J28.A F24.6 J28.A M24.3
Functional Diagram
DATA/ BUS BUFFER CLK 0 COUNTER 0 GATE 0 OUT 0 CONTROL WORD REGISTER RD WR A0 A1 CS CLK 2 CONTROL WORD REGISTER COUNTER 2 GATE 2 OUT 2 GATE n CLK n OUT n COUNTER INTERNAL BLOCK DIAGRAM READ/ WRITE LOGIC INTERNAL BUS COUNTER 1 CLK 1 GATE 1 OUT 1 CONTROL LOGIC CE STATUS LATCH CRM STATUS REGISTER CRL INTERNAL BUS
D7 - D0
8
OLM
OLL
Pin Description
SYMBOL D7 - D0 CLK 0 OUT 0 GATE 0 GND OUT 1 GATE 1 CLK 1 GATE 2 OUT 2 DIP PIN NUMBER 1-8 9 10 11 12 13 14 15 16 17 O I I I O TYPE I/O I O I DEFINITION DATA: Bi-directional three-state data bus lines, connected to system data bus. CLOCK 0: Clock input of Counter 0. OUT 0: Output of Counter 0. GATE 0: Gate input of Counter 0. GROUND: Power supply connection. OUT 1: Output of Counter 1. GATE 1: Gate input of Counter 1. CLOCK 1: Clock input of Counter 1. GATE 2: Gate input of Counter 2. OUT 2: Output of Counter 2.
4-2
82C54 Pin Description
SYMBOL CLK 2 A0, A1 DIP PIN NUMBER 18 19 - 20 (Continued) TYPE I I CLOCK 2: Clock input of Counter 2. ADDRESS: Select inputs for one of the three counters or Control Word Register for read/write operations. Normally connected to the system address bus. A1 0 0 1 1 CS RD WR VCC 21 22 23 24 I I I A0 0 1 0 1 SELECTS Counter 0 Counter 1 Counter 2 Control Word Register DEFINITION
CHIP SELECT: A low on this input enables the 82C54 to respond to RD and WR signals. RD and WR are ignored otherwise. READ: This input is low during CPU read operations. WRITE: This input is low during CPU write operations. VCC: The +5V power supply pin. A 0.1µF capacitor between pins VCC and GND is recommended for decoupling.
Functional Description
General The 82C54 is a programmable interval timer/counter designed for use with microcomputer systems. It is a general purpose, multi-timing element that can be treated as an array of I/O ports in the system software. The 82C54 solves one of the most common problems in any.