SN54/74LS256 DUAL 4-BIT ADDRESSABLE LATCH
The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common control inputs;...
SN54/74LS256 DUAL 4-BIT ADDRESSABLE LATCH
The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common control inputs; these include two Address inputs (A0, A1), an active LOW Enable input (E) and an active LOW Clear input (CL). Each latch has a Data input (D) and four outputs (Q0 – Q3). When the Enable (E) is HIGH and the Clear input (CL) is LOW, all outputs (Q0 – Q3) are LOW. Dual 4-channel demultiplexing occurs when the (CL) and E are both LOW. When CL is HIGH and E is LOW, the selected output (Q0 – Q3), determined by the Address inputs, follows D. When the E goes HIGH, the contents of the latch are stored. When operating in the addressable latch mode (E = LOW, CL = HIGH), changing more than one bit of the Address (A0, A1) could impose a transient wrong address. Therefore, this should be done only while in the memory mode (E= CL = HIGH).
DUAL 4-BIT ADDRESSABLE LATCH
LOW POWER
SCHOTTKY
Serial-to-Parallel Capability Output From Each Storage Bit Available Random (Addressable) Data Entry Easily Expandable Active Low Common Clear Input Clamp Diodes Limit High Speed Termination Effects
J SUFFIX CERAMIC CASE 620-09
16 1
16 1
N SUFFIX PLASTIC CASE 648-08
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 16 CL 15 E 14 Db 13 Q3b 12 Q2b 11 Q1b 10 Q0b 9
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 16 1
D SUFFIX SOIC CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC
1 A0
2 A1
3 Da
4...
