TF1004A

Data Sheet August 1999 LG1600FXH Clock and Data Regenerator Features s s s s s s s s s s Integrated clock recovery and data retiming Surface-mount package Single ECL supply Robust FPLL design Operation up to BER = 1e–3 SONET/SDH compatible loss of signal alarm High effective Q allows long run lengths Jitter tolerance exceeding ITU-T/Bellcore Low clock jitter generation: typical <0.005 UI Standard and custom data rates 0.50 Gbits/s—5.5 Gbits/s Complementary 50 Ω I/Os s Figure 1. LG1600FXH Open View Applications s SONET/SDH receiver terminals and regenerators OC-12 through OC-96/STM-4 through STM-32 SONET/SDH test equipment Proprietary bit rate systems Digital video transmission Clock doublers and quadruplers s s s s LG1600FXH Clock and Data Regenerator Data Sheet August 1999 Regenerated clock and data are available from complementary outputs that can either be ac coupled, to provide 50 Ω output match, or dc coupled with 50 Ω to ground at the receiving end. The second-order PLL filter bandwidth is set by the user with an external resistor between pin 11 and ground (required). An internal capacitor provides sufficient PLL damping for most applications. In critical applications, PLL damping can be increased using an external capacitor between pins 9 and 11. The device is powered by a single –5.2 V ECL compatible supply and typically consumes 1.5 W. The LG1600FXH comes in standard bit rates, but can be factory tuned for any rate between 500 Mbits/s and 5500 Mbits/s. A tes...