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TSL202R Dataheets PDF



Part Number TSL202R
Manufacturers ETC
Logo ETC
Description 128 *1 LINEAR SENSOR ARRAY
Datasheet TSL202R DatasheetTSL202R Datasheet (PDF)

t TSL202R 128 y 1 LINEAR SENSOR ARRAY t TAOS032B – AUGUST 2002 D D D D D D D D D 128 × 1 Sensor-Element Organization 200 Dots-Per-Inch (DPI) Sensor Pitch High Linearity and Uniformity Wide Dynamic Range . . . 2000:1 (66 dB) Output Referenced to Ground Low Image Lag . . . 0.5% Typ Operation to 5 MHz Single 5-V Supply Replacement for TSL202 (TOP VIEW) VDD 1 SI1 2 CLK 3 AO1 4 GND 5 SO2 6 NC 7 NC – No internal connection ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÇÇ ÇÇ ÇÇ ÇÇ ÇÇ 14 NC 13 SO1 12 GND 11 NC 10 SI2 9 NC 8 A.

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t TSL202R 128 y 1 LINEAR SENSOR ARRAY t TAOS032B – AUGUST 2002 D D D D D D D D D 128 × 1 Sensor-Element Organization 200 Dots-Per-Inch (DPI) Sensor Pitch High Linearity and Uniformity Wide Dynamic Range . . . 2000:1 (66 dB) Output Referenced to Ground Low Image Lag . . . 0.5% Typ Operation to 5 MHz Single 5-V Supply Replacement for TSL202 (TOP VIEW) VDD 1 SI1 2 CLK 3 AO1 4 GND 5 SO2 6 NC 7 NC – No internal connection ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÇÇ ÇÇ ÇÇ ÇÇ ÇÇ 14 NC 13 SO1 12 GND 11 NC 10 SI2 9 NC 8 AO2 Description The TSL202R linear sensor array consists of two sections of 64 photodiodes and associated charge amplifier circuitry arranged to form a contiguous 128 × 1 array. The pixels measure 120 µm (H) by 70 µm (W) with 125-µm center-to-center spacing and 55-µm spacing between pixels. Operation is simplified by internal control logic that requires only a serial-input (SI) signal and a clock. The TSL202R is intended for use in a wide variety of applications including mark detection and code reading, optical character recognition (OCR) and contact imaging, edge detection and positioning as well as optical linear and rotary encoding. Functional Block Diagram (each section — pin numbers apply to section 1) Pixel 1 Integrator Reset Pixel 2 Pixel 3 Pixel 64 Analog Bus Output Amplifier 4 AO Sample/ Output 5 GND RL (External 330 W Load) 1 VDD _ + Switch Control Logic Gain Trim Q3 Q64 Q1 Q2 CLK SI 3 2 64-Bit Shift Register The LUMENOLOGY r Company t Copyright E 2002, TAOS Inc. Texas Advanced Optoelectronic Solutions Inc. 800 Jupiter Road, Suite 205 S Plano, TX 75074 S (972) t 673-0759 www.taosinc.com 1 TSL202R 128 y 1 LINEAR SENSOR ARRAY TAOS032B – AUGUST 2002 Terminal Functions TERMINAL NAME AO1 AO2 CLK GND NC SI1 SI2 SO1 SO2 VDD NO. 4 8 3 5,12 7, 9, 11, 14 2 10 13 6 1 Analog output of section 1 Analog output of section 2 Clock. Clk controls charge transfer, pixel output, and reset. Ground (substrate). All voltages are referenced to GND. No internal connection Serial input (section 1). SI1 defines the start of the data-out sequence. Serial input (section 2). SI2 defines the start of the data-out sequence. Serial output (section 1). SO1 provides a signal to drive the SI2 input. Serial output (section 2). SO2 provides a signal to drive the SI input of another device for cascading or as an end-of-data indication. Supply voltage. Supply voltage for both analog and digital circuitry. DESCRIPTION Detailed Description The sensor consists of 128 photodiodes arranged in a linear array. Light energy impinging on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time. The integration time is the interval between two consecutive output periods. The output and reset of the integrators is controlled by a 128-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI for one positive going clock edge (see Figures1 and 2)†. As the SI pulse is clocked through the 128-bit shift register, the charge on the sampling capacitor of each pixel is sequentially connected to a charge-coupled output amplifier that generates a voltage output, AO. When the bit position goes low, the pixel integrator is reset. On the 129th clock rising edge, the SI pulse is clocked out of the shift register and the output assumes a high-impedance state. Note that this 129th clock pulse is required to terminate the output of the 128th pixel and return the internal logic to a known state. A subsequent SI pulse can be presented as early as the 130th clock pulse, thereby initiating another pixel output cycle. The voltage developed at analog output (AO) is given by: Vout = Vdrk + (Re) (Ee) (tint) where: Vout Vdrk Re Ee tint is is is is is the analog output voltage for white condition the analog output voltage for dark condition the device responsivity for a given wavelength of light given in V/(µJ/cm2) the incident irradiance in µW/cm2 integration time in seconds AO is driven by a source follower that requires an external pulldown resistor (330-Ω typical). The output is nominally 0 V for no light input, 2 V for normal white-level, and 3.4 V for saturation light level. When the device is not in the output phase, AO is in a high impedance state. A 0.1 µF bypass capacitor should be connected between VDD and ground as close as possible to the device. † For proper operation, after meeting the minimum hold time condition, SI must go low before the next rising edge of the clock. Copyright E 2002, TAOS Inc. t The LUMENOLOGY r Company t 2 www.taosinc.com TSL202R 128 y 1 LINEAR SENSOR ARRAY TAOS032B – AUGUST 2002 Absolute Maximum Ratings† Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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