UPD72107

DATA SHEET MOS INTEGRATED CIRCUIT µPD72107 LAP-B CONTROLLER Link Access Procedure Balanced mode The µPD72107 is an LSI that supports LAP-B protocol specified by the ITU-T recommended X.25 on a single chip. FEATURES Complied with ITU-T recommended X.25 (LAP-B84 edition) HDLC frame control Sequence control Flow control ITU-T recommended X.75 supported TTC standard JT-T90 supported Optional functions Option frame Global address frame Error check deletion frame Powerful test functions Data loopback function Loopback test link function Frame trace function Abundant statistical information Detailed mode setting function Modem control function On-chip DMAC (Direct Memory Access Controller) 24-bit address Byte/word transfer enabled (switch with external pin) Memory-based interface Memory-based command Memory-based status Memory-based transmit/receive data MAX.4 Mbps serial transfer rate NRZ, NRZI coding ORDERING INFORMATION Part Number Package 64-pin plastic shrink DIP (750 mils) 80-pin plastic QFP (14 x 14 mm) 68-pin plastic QFJ (950 x 950 mils) µPD72107CW µPD72107GC-3B9 µPD72107L The information in this document is subject to change without notice. Document No. S12962EJ5V0DS00 (5th edition) Date Published October 1998 N CP(K) Printed in Japan © 1998 µPD72107 BLOCK DIAGRAM D0-D7 A16D8 -A23D15 A0-A15 IORD IOWR MRD MWR UBE CS ASTB AEN READY HLDRQ HLDAK CRQ INT CLRINT B/W PU VCC GND RESET CLK TxC TxD Internal controller TxFIFO Transmitter RTS CTS Bu...