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VIS
Description
4 (word x bit x bank), respectively.
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
The VG36644041D, VG36648041D and VG36641641D are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 4,194,304 x 4 x 4, 2,097,152 x 8 x 4 and 1,048,576 x 16 x
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All input and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOPII.
Features
• Single 3.3V ( ± 0.3V ) power supply • High speed clock cycle time -6 : 166MHz<3-3-3>, available only on 4MX16 option -7 : 143MHz<3-3-3>, 133MHz<2-3-2> -7L: 133MHz<3-3-3> -8H: 100MHz<2-2-2> • Fully synchronous operation referenced to clock rising edge • Possible to assert random column access in every cycle • Quad internal banks controlled by A12 & A13 (Bank Select) • Byte control by LDQM and UDQM for VG36641641D • Programmable Wrap sequence (Sequential / Interleave) • Programmable burst length (1, 2, 4, 8 and full page) • Programmable /CAS latency (2 and 3) • Automatic precharge and controlled precharge • CBR (Auto) refresh and self refresh • X4, X8, X16 organization • LVTTL compatible inputs and outputs • 4,096 refresh cycles / 64ms • Burst termination by Burst stop and Precharge command
Document :1G5-0177
Rev.2
Page 1
VIS
Pin Configurations
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
VG36644041 ( x4 ) VG36648041 ( x8 ) VG36641641 ( x16 ) VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC VDD NC /WE /CAS /RAS /CS A13/BA0 A12/BA1 A10 A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC VDD NC WE /CAS /RAS /CS A13/BA0 A12/BA1 A10 A0 A1 A2 A3 VDD VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE /CAS /RAS /CS A13/BA0 A12/BA1 A10 A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC
VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC VSS NC DQM CLK CKE NC
VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC VSS NC DQM CLK CKE NC
A11
A9 A8 A7 A6 A5 A4 VSS
A11
A9 A8 A7 A6 A5 A4 VSS
A11
A9 A8 A7 A6 A5 A4 VSS
Pin Descriptions Pin Name CLK CKE /CS /RAS
/CAS /WE DQ0 ~ DQ15
Function Master Clock Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data I/O
Pin Name DQM A0-11 BA0,1 VDD VDDQ VSS VSSQ
Function DQ Mask Enable Address Input Bank Address Power Supply Power Supply for DQ Ground Ground for DQ
Document :1G5-0177
Rev.2
Page 2
VIS
Block Diagram
CLK CKE Clock Generator
VG36644041DT / VG36648041DT / VG36641641DT CMOS Synchronous Dynamic RAM
Address
Mode Register
Row Decoder
Row Address Buffer & Refresh Counter
Bank D Bank C Bank B
Bank A
Command Decoder.