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VC16374ADGG Dataheets PDF



Part Number VC16374ADGG
Manufacturers NXP
Logo NXP
Description 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs 3-State
Datasheet VC16374ADGG DatasheetVC16374ADGG Datasheet (PDF)

INTEGRATED CIRCUITS 74LVC16374A/74LVCH16374A 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State) Product specification Supersedes data of 1997 Aug 22 IC24 Data Handbook 1998 Mar 17 Philips Semiconductors Philips Semiconductors Product specification 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State) 74LVC16374A/ 74LVCH16374A FEATURES • 5 volt tolerant inputs/outputs for interfacing with 5V logic • Wide supply voltage range.

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INTEGRATED CIRCUITS 74LVC16374A/74LVCH16374A 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State) Product specification Supersedes data of 1997 Aug 22 IC24 Data Handbook 1998 Mar 17 Philips Semiconductors Philips Semiconductors Product specification 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State) 74LVC16374A/ 74LVCH16374A FEATURES • 5 volt tolerant inputs/outputs for interfacing with 5V logic • Wide supply voltage range of 1.2 V to 3.6 V • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • MULTIBYTETM flow-through standard pin-out architecture • Low inductance multiple power and ground pins for minimum noise and ground bounce PIN CONFIGURATION 1OE 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 1 2 3 4 5 6 7 8 9 48 1CP 47 1D0 46 1D1 45 GND 44 1D2 43 1D3 42 VCC 41 1D4 40 1D5 39 GND 38 1D6 37 1D7 36 2D0 35 2D1 34 GND 33 2D2 32 2D3 31 VCC 30 2D4 29 2D5 28 GND 27 2D6 26 2D7 25 2CP • Direct interface with TTL levels • All data inputs have bus hold (74LVCH16374A only) • High impedance when VCC = 0 DESCRIPTION The 74LVC(H)16374A is a 16-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-State outputs for bus oriented applications. The 74LVC16374A consists of 2 sections of eight positive edge-triggered flip-flops. A clock (CP) input and an output enable (OE) are provided for each octal. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. These features allow the use of these devices in a mixed 3.3V/5V environment. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The 74LVCH16374A bus hold data inputs eliminates the need for external pull up resistors to hold unused inputs. GND 10 1Q6 11 1Q7 12 2Q0 13 2Q1 14 GND 15 2Q2 16 2Q3 17 VCC 18 2Q4 19 2Q5 20 GND 21 2Q6 22 2Q7 23 2OE 24 SW00074 QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL tPHL/tPLH fMAX CI CPD PARAMETER Propagation delay Cp to Qn Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop VCC = 3.3V1 CL = 50pF VCC = 3.3V CONDITIONS TYPICAL 3.8 150 5.0 30 UNIT ns MHz pF pF NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs. ORDERING INFORMATION PACKAGES 48-Pin Plastic SSOP Type III 48-Pin Plastic TSSOP Type II 48-Pin Plastic SSOP Type III 48-Pin Plastic TSSOP Type II TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C OUTSIDE NORTH AMERICA 74LVC16374A DL 74LVC16374A DGG 74LVCH16374A DL 74LVCH16374A DGG NORTH AMERICA VC16374A DL VC16374A DGG VCH16374A DL VCH16374A DGG DWG NUMBER SOT370-1 SOT362-1 SOT370-1 SOT362-1 1998 Mar 17 2 853-2028 19111 Philips Semiconductors Product specification 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State) 74LVC16374A/ 74LVCH16374A PIN DESCRIPTION PIN NUMBER 1 2, 3, 5, 6, 8, 9, 11, 12 4, 10, 15, 21, 28, 34, 39, 45 7, 18, 31, 42 13, 14, 16, 17, 19, 20, 22, 23 24 25 36, 35, 33, 32, 30, 29, 27, 26 47, 46, 44, 43, 41, 40, 38, 37 48 SYMBOL 1OE 1Q0 to 1Q7 GND VCC 2Q0 to 2Q7 2OE 2CP 2D0 to 2D7 1D0 to 1D7 1CP NAME AND FUNCTION Output enable input (active LOW) LOGIC SYMBOL 1 24 1OE 47 2OE 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 3-State flip-flop outputs Ground (0V) Positive supply voltage 3-State flip-flop outputs Output enable input (active LOW) Clock input Data inputs Data inputs Clock input 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 1CP 2CP 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 48 25 SW00075 LOGIC DIAGRAM 1D0 D CP FF1 Q 1Q0 2D0 D CP FF9 Q 2Q0 1CP 1OE 2CP 2OE TO 7 OTHER CHANNELS TO 7 OTHER CHANNELS SW00076 FUNCTION TABLE INPUTS OPERATING MODES nOE Load and read register Load register and disable outputs L L H H nCP ° ° ° ° nDx l h l h INTERNAL FLIP-FLOPS L H L H OUTPUTS Q0 to Q7 L H Z Z H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition Z = high impedance OFF-state ° = LOW-to-HIGH CP transition 1998 Mar 17 3 Philips Semiconductors Product specification 16-bit edge triggered D-type flip-flop with 5 Volt tolerant inputs/outputs (3-State) 74LVC16374A/ 74LVCH16374A LOGIC SYMBOL (IEEE/IEC) 1OE 1CLK 2OE 2CLK 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 1.


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