V62C3802048L

V62C3802048L(L) Ultra Low Power 256K x 8 CMOS SRAM Features Low-power consumption - Active: 40mA at 35ns - Stand-by: 10 µA (CMOS input/output) 2 µA CMOS input/output, L version Single + 2.7 to 3.3V Power Supply Equal access and cycle time 35/45/55/70/85/100 ns access time Easy memory expansion with CE1, CE2 and OE inputs 1.0V data retention mode TTL compatible, Tri-state input/output Automatic power-down when deselected Package available: 32-TSOP1 / STSOP 48 Ball CSP_BGA Logic Block Diagram Functional Description The V62C3802048L is a low power CMOS Static RAM organized as 262,144 words by 8 bits. Easy memory expansion is provided by an active LOW CE1, an active HIGH CE2, an active LOW OE , and Tri-state I/O’s. This device has an automatic power-down mode feature when deselected. Writing to the device is accomplished by taking Chip Enable 1 (CE1) with Write Enable (WE ) LOW, and Chip Enable 2 (CE2) HIGH. Reading from the device is performed by taking Chip Enable 1 (CE1) with Output Enable (OE) LOW while Write Enable (WE ) and Chip Enable 2 (CE2) is HIGH. The I/O pins are placed in a high-impedance state when the device is deselected: the outputs are disabled during a write cycle. The V62C3802048LL comes with a 1V data retention feature and Lower Standby Power. The V62C3802048L is available in a 32-pin 8 x 20 mm TSOP1/8 x 13.4mm STSOP and CSP type 48-fpBGA packages. 32-Pin TSOP1 / STSOP(CSP_BGA see next page) A11 A9 A8 INPUT BUFFER ROW DECODER SENSE ...