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V62C1164096 Dataheets PDF



Part Number V62C1164096
Manufacturers Mosel Vitelic Corp
Logo Mosel Vitelic  Corp
Description 256K x 16/ CMOS STATIC RAM
Datasheet V62C1164096 DatasheetV62C1164096 Datasheet (PDF)

MOSEL VITELIC Features s s s s s s s s V62C1164096 256K x 16, CMOS STATIC RAM PRELIMINARY Description The V62C1164096 is a 4,194,304-bit static random-access memory organized as 262,144 words by 16 bits. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. High-speed: 85, 100 ns Ultra low CMOS standby current of 2µA (max.) Fully static operation All inputs and outputs directly TTL compatible Three state outputs Ultra low data r.

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MOSEL VITELIC Features s s s s s s s s V62C1164096 256K x 16, CMOS STATIC RAM PRELIMINARY Description The V62C1164096 is a 4,194,304-bit static random-access memory organized as 262,144 words by 16 bits. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. High-speed: 85, 100 ns Ultra low CMOS standby current of 2µA (max.) Fully static operation All inputs and outputs directly TTL compatible Three state outputs Ultra low data retention current (VCC = 1.0V) Operating voltage: 1.8V – 2.3V Packages – 48-Ball CSP BGA (8mm x 10mm) Functional Block Diagram A0 A6 A7 A8 A9 I/O1 Input Data Circuit I/O16 A10 UBE LBE OE WE CE1 CE2 A17 Row Decoder 1024 x 4096 Memory Array VCC GND Column I/O Column Decoder Control Circuit Device Usage Chart Package Outline Operating Temperature Range 0°C to 70°C –40°C to +85°C B • • Access Time (ns) 85 • • 100 • • L • Power LL • • Temperature Mark Blank I V62C1164096 Rev. 1.0 November 2001 1 MOSEL VITELIC Pin Descriptions A 0–A17 Address Inputs These 18 address inputs select one of the 256K x 16 bit segments in the RAM. CE1, CE2 Chip Enable Inputs CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The I/O pins will be in the high-impedance state when deselected. OE Output Enable Input The output enable input is active LOW. With the chip enabled, when OE is Low and WE High, data will be presented on the I/O pins. The I/O pins will be in the high impedance state when OE is High. V62C1164096 UBE, LBE Byte Enable Active low inputs. These inputs are used to enable the upper or lower data byte. Write Enable Input WE The write enable input is active LOW and controls read and write operations. With the chip enabled, when WE is HIGH and OE is LOW, output data will be present at the I/O pins; when WE is LOW and OE is HIGH, the data present on the I/O pins will be written into the selected memory locations. I/O1–I/O16 Data Input and Data Output Ports These 16 bidirectional ports are used to read data from and write data into the RAM. VCC GND Power Supply Ground Pin Configurations (Top View) 48 BGA 1 A B C D E F G H 2 3 4 5 6 A B 1 BLE I/O9 2 OE BHE 3 A0 A3 4 A1 A4 A6 A7 5 A2 6 CE2 CE1 I/O1 I/O2 I/O3 I/O4 VCC C I/O10 I/O11 A5 D E F VSS I/O12 A17 VCC I/O13 NC A16 I/O5 VSS I/O15 I/O14 A14 A15 I/O6 I/O7 NC A8 A12 A13 A9 WE I/O8 NC G I/O16 H NC A10 A11 Note: NC means no connect. TOP VIEW TOP VIEW V62C1164096 Rev. 1.0 November 2001 2 MOSEL VITELIC Part Number Information V MOSEL-VITELIC MANUFACTURED V62C1164096 62 C 18 16 4096 – TEMP. SRAM FAMILY OPERATING VOLTAGE DENSITY 4096K PWR. SPEED PKG BLANK = 0°C to 70°C I = -40°C to +85°C 85 ns 100 ns B = BGA 62 = STANDARD C = CMOS PROCESS 18 = 1.8V – 2.3V ORGANIZATION 16 = 16-bit L = LOW POWER LL = DOUBLE LOW POWER Absolute Maximum Ratings (1) S.


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