V61C51161024

MOSEL VITELIC V61C51161024 64K x 16 HIGH SPEED STATIC RAM PRELIMINARY Features s s s s s s High-speed: 10, 12, 15 ns All inputs and outputs directly TTL compatible Three state outputs Byte Control Pins Single 5V ± 10% Power Supply Packages – 44-pin TSOP (Standard) – 44-pin 400 mil SOJ Description The V61C51161024 is a 1,048,576-bit static random-access memory organized as 65,536 words by 16 bits. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Functional Block Diagram A1 Row Decoder Memory Array VCC GND A7 A8 A9 I/O0 Input Data Circuit I/O15 A0 UBE LBE OE WE CE Column I/O Column Decoder A10 A15 Control Circuit 6151161024-01 Device Usage Chart Operating Temperature Range 0°C to 70 °C Package Outline T K 10 Access Time (ns) 12 15 Temperature Mark Blank V61C51161024 Rev. 1.0 July 1998 1 MOSEL VITELIC Pin Descriptions A0–A15 Address Inputs These 16 address inputs select one of the 64K x 16 bit segments in the RAM. CE Chip Enable Input CE is active LOW. It must be active to read from or write to the device. If chip enable is not active, the device is deselected and is in a standby power mode. The I/O pins will be in the high-impedance state when deselected. OE Output Enable Input The output enable input is active LOW. When OE is Low with CE Low and WE High, data will be presented on the I/O pins. The I/O pins will be in the high impedance state when OE is High. V61C51161024 UBE, LEB B...