V54C365324V

MOSEL VITELIC V54C365324V 200/183/166/143 MHz 3.3 VOLT ULTRA HIGH PERFORMANCE 2M X 32 SDRAM 4 BANKS X 512Kbit X 32 PRELIMINARY V54C365324V Clock Frequency (tCK) CAS Latency Cycle Time (tCK) Access Time (tAC ) -5 200 3 5 5 -55 183 3 5.5 5.5 -6 166 3 6 6 -7 143 3 7 6 -8 125 3 8 6 Unit MHz clocks ns ns Features s JEDEC Standard 3.3V Power Supply s The V54C365324V is ideally suited for high performance graphics peripheral applications s Single Pulsed RAS Interface s Programmable CAS Latency: 2, 3 s All Inputs are sampled at the positive going edge of clock s Programmable Wrap Sequence: Sequential or Interleave s Programmable Burst Length: 1, 2, 4, 8 and Full Page for Sequential and 1, 2, 4, 8 for Interleave s DQM 0-3 for Byte Masking s Auto & Self Refresh s 2K Refresh Cycles/32 ms s Burst Read with Single Write Operation Description The V54C365324V is a 67,108, 864 bits synchronous high data rate DRAM organized as 4 x 524,288 words by 32 bits. The device is designed to comply with JEDEC standards set for synchronous DRAM products, both electrically and mechanically. Synchronous design allows precise cycle control with the system clock. The CAS latency, burst length and burst sequence must be programmed into device prior to access operation. V54C365324V Rev. 1.2 August 2001 1 MOSEL VITELIC PIN CONFIGURATION VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 WE CAS RAS CS NC BA0 BA1 A10/AP A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ D...