Document
VIC068A
VMEbus Interface Controller
Features
• Complete VMEbus interface controller and arbiter — 58 internal registers provide configuration control and status of VMEbus and local operations — Drives arbitration, interrupt, address modifier utility, strobe, address lines A07 through A01 and data lines D07 through D00 directly, and provides signals for control logic to drive remaining address and data lines — Direct connection to 68xxx family and mappable to non-68xxx processors Complete master/slave capability • — Supports read, write, write posting, and block transfers — Accommodates VMEbus timing requirements with internal digital delay line (1⁄ 2-clock granularity) — Programmable metastability delay — Programmable data acquisition delays — Provides timeout timers for local bus and VMEbus transactions Interleaved block transfers over VMEbus • — Acts as DMA master on local bus — Programmable burst count, transfer length, and interleaved period interval — Supports local module-based DMA Arbitration support • — Supports single-level, priority and round robin arbitration — Supports fair request option as requester • Interrupt support — Complete support for the VMEbus interrupts: interrupter and interrupt handler — Seven local interrupt lines — 8-level interrupt priority encode — Total of 29 interrupts mapped through the VIC068A • Miscellaneous features — Refresh option for local DRAM — Four broadcast location monitors — Four module-specific location monitors — Eight interprocessor communications registers — PGA or QFP packages — Compatible with IEEE Specification 1014, Rev. C — Supports RMC operations • See the VMEbus Interface Handbook for more information
Functional Description
The VMEbus interface controller (VIC068A) is a single chip designed to minimize the cost and board area requirements and to maximize performance of the VMEbus interface of a VMEbus master/slave module. This can be implemented on VIC068A either an 8-bit, 16-bit, or 32-bit VMEbus system. The VIC068A performs all VMEbus system controller functions plus many others, which simplify the development of VIC068Aa VMEbus interface. The VIC068A utilizes patented on-chip output buffers. These CMOS high-drive buffers provide direct connection to the address and data lines. In addition to these signals, the VIC068A connects directly to the arbitration, interrupt, address modifier, utility and strobe lines. Signals are provided which control data direction and latch functions needed for a 32-bit implementation. The VIC068A was developed through the efforts of a consortium of board vendors, under the auspices of the VMEbus International Trade Association (VITA). The VIC068A thus insures compatibility between boards designed by different manufacturers.
Cypress Semiconductor Corporation
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3901 North First Street
•
San Jose • CA 95134 • 408-943-2600 December 1990 - Revised July 23, 1997
VIC068A
Pin Configurations
Pin Grid Array (PGA) Bottom View
A B C D E F G H J K L M N P R
GND
IPL2*
LIACKO*
LIRQ2*
LIRQ5*
ASIZ1
ASIZ0
SLSEL1*
WORD*
FIACK*
A02
A04
VCC
GND
IRQ4*
LD6
BLT*
IPL1*
VCC
LIRQ1*
LIRQ4*
LIRQ6*
ICFSEL*
MWB*
A01
A03
A05
A07
IRQ3*
IRQ7*
LD2
LD5
DEDLK*
IPL0*
LAEN
LIRQ3*
LIRQ7*
GND
SLSEL0*
GND
A06
IRQ1*
IRQ2*
IRQ6*
ACFAIL*
LD1
LD3
LD7
LOCATOR PIN
IRQ5*
VCC
IACKOUT*
LA7
LD0
LD4
SYSFAIL* SYSRESET* DTACK*
LA3
LA5
LA6
IACKIN*
IACK*
AM0
LA2
LA4
GND
GND
AS*
AM1
LA1
LA0
VCC
GND
AM2
AM3
CS*
DSACK1*
DS*
VCC
LWORD*
AM4
PAS*
LBERR*
RESET*
BERR*
WRITE*
AM5
DSACK0*
R/W*
FC1
BR2*
DS1*
DS0*
HALT*
RMC*
LBR*
BBSY*
BR1*
BR0*
FC2
SIZ0
SCON*
CLK64M
LADI
GND
VCC
GND
VCC
D00
BGOUT1*
BGIN2*
BGIN0*
BR3*
GND
SIZ1
IRESET*
LADO
LEDI
DDIR
LWDENIN*
DENO*
D06
D03
D01
GND
BGOUT0*
BGIN3*
BGIN1*
BCLR*
LBG*
ABEN*
VCC
LEDO
UWDENIN* SWDEN*
ISOBE*
D07
D05
D04
D02
BGOUT3*
BGOUT2*
SYSCLK
GND
VIC068A–1
2
VIC068A
Pin Configurations (continued)
160-Pin Quad Flatpack (QFP) Top View
VCC VCC GND BLT* DEDLK* LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0 LA7 LA6 LA5 LA4 LA3 LA2 GND VCC LA1 LA0 CS* PAS* DS* DSACK1* DSACK0* LBERR* RESET* HALT* R/W* FC2 FC1 RMC* SIZ1 SIZ0 LBR* VCC VCC GND GND IPL0* IPL1* IPL2* VCC LAEN LIAKO* LIRQ1* LIRQ2* LIRQ3* LIRQ4* LIRQ5* LIRQ6* LIRQ7* ASIZ1* ASIZ0* ICFSEL* SLSEL1* GND SLSEL0* WORD* FCIACK* MWB* A1 GND A2 A3 A4 VCC A5 A6 A7 VSS IRQ1* IRQ2* IRQ3* IRQ4* GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
GND GND LBG* IRESET* SCON* CLK64M ABEN* LADO LADI LEDI VCC LEDO DDIR UWDENIN* GND LWDENIN* DENO* SWDEN* ISOBE* VCC GND D07 D06 D05 D04 VCC D03 D02 D01 D00 BGOUT3* .