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X25650 Dataheets PDF



Part Number X25650
Manufacturers Xicor
Logo Xicor
Description 5MHz SPI Serial E 2 PROM with Block Lock TM Protection
Datasheet X25650 DatasheetX25650 Datasheet (PDF)

64K X25650 5MHz SPI Serial E2PROM with Block LockTM Protection 8K x 8 Bit FEATURES DESCRIPTION The X25650 is a CMOS 65,536-bit serial E2PROM, internally organized as 8K x 8. The X25650 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to sh.

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64K X25650 5MHz SPI Serial E2PROM with Block LockTM Protection 8K x 8 Bit FEATURES DESCRIPTION The X25650 is a CMOS 65,536-bit serial E2PROM, internally organized as 8K x 8. The X25650 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The X25650 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25650 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. The WP input can be used as a hardwire input to the X25650 disabling all write attempts to the status register, thus providing a mechanism for limiting end user capability of altering 0, 1/4, 1/2 or all of the memory. The X25650 utilizes Xicor’s proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. • • • • • • • • • • • 5MHz Clock Rate Low Power CMOS <1µA Standby Current <5mA Active Current 2.5V To 5.5V Power Supply SPI Modes (0,0 & 1,1) 8K X 8 Bits 32 Byte Page Mode Block Lock™ Protection Protect 1/4, 1/2 or all of E2PROM Array Programmable Hardware Write Protection In-Circuit Programmable ROM Mode Built-in Inadvertent Write Protection Power-Up/Down protection circuitry Write Enable Latch Write Protect Pin Self-Timed Write Cycle 5ms Write Cycle Time (Typical) High Reliability Endurance: 100,000 cycles Data Retention: 100 Years ESD protection: 2000V on all pins Packages 8-Lead SOIC 20-Lead TSSOP FUNCTIONAL DIAGRAM ST ATUS REGISTER WRITE PROTECT LOGIC X DECODE LOGIC 64 64 X 256 SO SI SCK CS HOLD COMMAND DECODE AND CONTROL LOGIC 64 64 X 256 8K BYTE ARRAY 128 128 X 256 WP WRITE CONTROL AND TIMING LOGIC 32 8 Y DECODE DATA REGISTER Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc. ©Xicor, Inc. 1994, 1995, 1996 Patents Pending 7037–1.5 6/19/97 T1/C0/D0 SH 1 7037 FRM F01 Characteristics subject to change without notice X25650 PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) When CS is HIGH, the X25650 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway, the X25650 will be in the standby power mode. CS LOW enables the X25650, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is LOW and the nonvolatile bit WPEN is “1”, nonvolatile writes to the X25650 status register are disabled, but the part otherwise functions normally. When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW while CS is still LOW will interrupt a write to the PIN NAMES Symbol CS SO SI SCK X25650 status register. If the internal write cycle has already been initiated, WP going LOW will have no affect on a write. The WP pin function is blocked when the WPEN bit in the status register is “0”. This allows the user to install the X25650 in a system with WP pin grounded and still be able to write to the status register. The WP pin functions will be enabled when the WPEN bit is set “1”. Hold (HOLD) HOLD is used in conjunction with the CS pin to pause the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause PIN CONFIGURATION NOT TO SCALE SOIC CS 0.197" Max SO WP V SS 1 2 3 4 0.244" X25650 8 7 6 5 V CC HOLD SCK SI TSSOP NC CS SO SO NC NC WP VSS NC NC 1 2 3 4 5 6 7 8 9 10 20 20 19 19 18 18 17 17 16 16 X25650 15 15 14 14 13 13 12 12 11 11 0.252" 7037 FRM F02 NC VCC HOLD HOLD NC NC SCK SI NC NC Description Chip Select Input Serial Output Serial Input Serial Clock Input Write Protect Input Ground Supply Voltage Hold Input No Connect 7037 FRM T01 0.300" Max WP VSS VCC HOLD NC * Pin 2 and Pin 3 are internally connected. Only one CS needs to be connected externally. 2 X25650 the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be.


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