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X25320 Dataheets PDF



Part Number X25320
Manufacturers Xicor
Logo Xicor
Description SPI Serial E2PROM With Block LockTM Protection
Datasheet X25320 DatasheetX25320 Datasheet (PDF)

APPLICATION NOTE A V A I L A B L E X25320 32K AN61 X25320 SPI Serial E2PROM With Block LockTM Protection DESCRIPTION 4K x 8 Bit FEATURES • 2MHz Clock Rate • SPI Modes (0,0 & 1,1) • 4K X 8 Bits — 32 Byte Page Mode • Low Power CMOS — <1µA Standby Current — <5mA Active Current During Write • 2.7V To 5.5V Power Supply • Block Lock Protection — Protect 1/4, 1/2 or all of E2PROM Array • Built-in Inadvertent Write Protection — Power-Up/Power-Down protection circuitry — Write Enable Latch — Write P.

  X25320   X25320



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APPLICATION NOTE A V A I L A B L E X25320 32K AN61 X25320 SPI Serial E2PROM With Block LockTM Protection DESCRIPTION 4K x 8 Bit FEATURES • 2MHz Clock Rate • SPI Modes (0,0 & 1,1) • 4K X 8 Bits — 32 Byte Page Mode • Low Power CMOS — <1µA Standby Current — <5mA Active Current During Write • 2.7V To 5.5V Power Supply • Block Lock Protection — Protect 1/4, 1/2 or all of E2PROM Array • Built-in Inadvertent Write Protection — Power-Up/Power-Down protection circuitry — Write Enable Latch — Write Protect Pin • Self-Timed Write Cycle — 5ms Write Cycle Time (Typical) • High Reliability — Endurance: 100,000 cycles — Data Retention: 100 Years — ESD protection: 2000V on all pins • 8-Lead PDlP Package • 8-Lead SOIC Package • 14-Lead TSSOP Package FUNCTIONAL DIAGRAM STATUS REGISTER WRITE PROTECT LOGIC The X25320 is a CMOS 32768-bit serial E2PROM, internally organized as 4K x 8. The X25320 features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The bus signals are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a chip select (CS) input, allowing any number of devices to share the same bus. The X25320 also features two additional inputs that provide the end user with added flexibility. By asserting the HOLD input, the X25320 will ignore transitions on its inputs, thus allowing the host to service higher priority interrupts. The WP input can be used as a hardwire input to the X25320 disabling all write attempts to the status register, thus providing a mechanism for limiting end user capability of altering 0, 1/4, 1/2 or all of the memory. The X25320 utilizes Xicor’s proprietary Direct Write™ cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. X DECODE LOGIC 32 4K BYTE ARRAY 32 X 256 SO SI SCK CS HOLD COMMAND DECODE AND CONTROL LOGIC 32 32 X 256 64 64 X 256 WP WRITE CONTROL AND TIMING LOGIC 32 8 Y DECODE DATA REGISTER 3063 ILL F01 Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc. ©Xicor, Inc. 1994, 1995, 1996 Patents Pending 3063-3.9 6/11/96 T4/C1/D0 NS 1 Characteristics subject to change without notice X25320 PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) When CS is HIGH, the X25320 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway, the X25320 will be in the standby power mode. CS LOW enables the X25320, placing it in the active power mode. It should be noted that after power-on, a HIGH to LOW transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is LOW and the nonvolatile bit WPEN is “1”, nonvolatile writes to the X25320 status register are disabled, but the part otherwise functions normally. When WP is held HIGH, all functions, including nonvolatile writes operate normally. WP going LOW while CS is still LOW will interrupt a write to the X25320 status register. If the internal write cycle has already been initiated, WP going LOW will have no effect on a write. The WP pin function is blocked when the WPEN bit in the status register is “0”. This allows the user to install the X25320 in a system with WP pin grounded and still be able to write to the status register. The WP pin functions will be enabled when the WPEN bit is set “1”. Hold (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. PIN CONFIGURATION DIP/SOIC CS SO WP VSS 1 2 3 4 X25320 8 7 6 5 VCC HOLD SCK SI TSSOP CS SO NC NC NC WP VSS 1 2 3 4 5 6 7 14 13 12 X25320 11 10 9 8 VCC HOLD NC NC NC SCK SI 3063 ILL F02.2 PIN NAMES SYMBOL CS SO SI SCK WP VSS VCC HOLD NC DESCRIPTION Chip Select Input Serial Output Serial Input Serial Clock Input Write Protect Input Ground Supply Voltage Hold Input No Connect 3063 PGM T01 2 X25320 PRINCIPLES OF OPERATION The X25320 is a 4K x 8 designed to interface directly with the synchronous serial peripheral interface (SPI) of many popular m.


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