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XC95288XV Dataheets PDF



Part Number XC95288XV
Manufacturers Xilinx
Logo Xilinx
Description High-Performance CPLD
Datasheet XC95288XV DatasheetXC95288XV Datasheet (PDF)

0 R XC95288XV High-Performance CPLD 0 5 DS050 (v2.2) August 27, 2001 Advance Product Specification Features • • 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins) - 208-pin PQFP (168 user I/O pins) - 280-pin CSP (192 user I/O pins) - 256-pin FBGA (192 user I/O pins) Optimized for high-performance 2.5V systems - Low power operation - Multi-voltage operation Advanced system features - In-system programmable - Four separate output ba.

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0 R XC95288XV High-Performance CPLD 0 5 DS050 (v2.2) August 27, 2001 Advance Product Specification Features • • 288 macrocells with 6,400 usable gates Available in small footprint packages - 144-pin TQFP (117 user I/O pins) - 208-pin PQFP (168 user I/O pins) - 280-pin CSP (192 user I/O pins) - 256-pin FBGA (192 user I/O pins) Optimized for high-performance 2.5V systems - Low power operation - Multi-voltage operation Advanced system features - In-system programmable - Four separate output banks - Superior pin-locking and routability with FastCONNECT II™ switch matrix - Extra wide 54-input Function Blocks - Up to 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with three global and one product-term clocks - Individual output enable per output pin - Input hysteresis on all user and boundary-scan pin inputs - Bus-hold ciruitry on all user pin inputs - Full IEEE Standard 1149.1 boundary-scan (JTAG) Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability - Endurance exceeding 10,000 program/erase cycles - 20 year data retention - ESD protection exceeding 2,000V Power Estimation Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XV device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power. For a general estimate of ICC, the following equation may be used: ICC (mA) = MCHP(0.36) + MCLP(0.23) + MC(0.005 mA/MHz) f Where: MCHP = Macrocells in high-performance (default) mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) This calculation is based on typical operating conditions using a pattern of 16-bit up/down counters in each Function Block with no output loading. The actual ICC value varies with the design application and should be verified during normal system operation. Figure 1 shows the above estimation in a graphical form. 450 400 350 • • • • • • 200 MHz Typical ICC (mA) 300 250 200 150 100 50 0 50 100 150 200 250 Description The XC95288XV is a 2.5V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of 16 54V18 Function Blocks, providing 6,400 usable gates with propagation delays of 5 ns. Hi g hP Lo or e rf ma nc e 120 MHz er wP ow Clock Frequency (MHz) DS050_01_012501 Figure 1: Typical ICC vs. Frequency for XC95288XV © 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS050 (v2.2) August 27, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 1 XC95288XV High-Performance CPLD R 3 JTAG Port 1 JTAG Controller In-System Programming Controller 54 I/O I/O I/O FastCONNECT II Switch Matrix I/O 54 18 18 Function Block 1 Macrocells 1 to 18 Function Block 2 Macrocells 1 to 18 I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 4 I/O/GTS 54 18 Function Block 3 Macrocells 1 to 18 54 18 Function Block 4 Macrocells 1 to 18 54 18 Function Block 16 Macrocells 1 to 18 DS055_02_101300 Figure 2: XC95288XV Architecture (Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.) 2 www.xilinx.com 1-800-255-7778 DS050 (v2.2) August 27, 2001 Advance Product Specification R XC95288XV High-Performance CPLD Absolute Maximum Ratings Symbol VCC VCCIO VIN VTS TSTG TSOL TJ Description Supply voltage relative to GND Supply voltage for output drivers Input voltage relative to GND(1) Value –0.5 to 2.7 –0.5 to 3.6 –0.5 to 3.6 –0.5 to 3.6 –65 to +150 +260 +150 Units V V V V oC oC oC Voltage applied to 3-state output(1) Storage temperature (ambient) Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) Junction temperature Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to –2.0V or overshoot to +3.6V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operation Conditions Symbol VCCINT Parameter Supply voltage for interna.


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