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XC95144XL

Xilinx

High Performance CPLD


Description
0 R XC95144XL High Performance CPLD DS056 (v2.0) April 3, 2007 00 Features 5 ns pin-to-pin logic delays System frequency up to 178 MHz 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins) - 144-CSP (117 user I/O pins) - Pb-free available for all packages ...



Xilinx

XC95144XL

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