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Z86C97 Dataheets PDF



Part Number Z86C97
Manufacturers Zilog.
Logo Zilog.
Description CMOS Z8 MICROCONTROLLER
Datasheet Z86C97 DatasheetZ86C97 Datasheet (PDF)

Z86C27/C97 CPS DC-2974-04 CUSTOMER PRODUCT SPECIFICATION Z86C27-ROM Z86C97-ROMLESS CMOS Z8® 8-BIT MICROCONTROLLER GENERAL DESCRIPTION The Z86C27 and Z86C97 Digital Television Controller (DTC) introduce a new level of sophistication to single-chip architecture. The Z86C27/C97 are members of the Z8 single-chip microcontroller family with 8 Kbytes of ROM (Z86C27), ROMless (Z86C97) and 236 bytes of RAM. Both devices are housed in a 64-pin DIP package, and are CMOS compatible. Having the ROM/ROMles.

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Z86C27/C97 CPS DC-2974-04 CUSTOMER PRODUCT SPECIFICATION Z86C27-ROM Z86C97-ROMLESS CMOS Z8® 8-BIT MICROCONTROLLER GENERAL DESCRIPTION The Z86C27 and Z86C97 Digital Television Controller (DTC) introduce a new level of sophistication to single-chip architecture. The Z86C27/C97 are members of the Z8 single-chip microcontroller family with 8 Kbytes of ROM (Z86C27), ROMless (Z86C97) and 236 bytes of RAM. Both devices are housed in a 64-pin DIP package, and are CMOS compatible. Having the ROM/ROMless selectivity, the DTC offers both external memory and pre-programmed ROM which enables the Z8 microcontroller to be used in a high volume production application device embedded with a custom program (customer supplied program). The Z86C97 ROMless offers the use of external memory rather than a preprogrammed ROM. This enables the Z8 microcontroller to be used in prototyping, low volume applications or where code flexibility is required. Zilog’s DTC offers fast execution, efficient use of memory, sophisticated interrupts, input/output bit manipulation capabilities, and easy hardware/software system expansion along with low cost and low power consumption. The device provides an ideal performance and reliability solution for consumer and industrial television applications. The Z86C27/C97 architecture is characterized by utilizing Zilog’s advanced Superintegration™ design methodology. The devices have an 8-bit internal data path controlled by a Z8 microcontroller, and On Screen Display (OSD) logic circuits/Pulse Width Modulators (PWM). Onchip peripherals include two register mapped I/O ports (Ports 2 and Port 3), Interrupt control logic (1 software, 2 external and 3 internal interrupts) and a standby mode recovery input port (Port 3, pin P30). The OSD control circuits support 8 rows by 20 columns for 128 kinds of characters. The character color is specified by row. One of the 8 rows is assigned to show two kinds of colors for bar type displays such as volume control. The OSD is capable of displaying either low resolution (5x7 dot pattern) or high resolution (11x15 dot pattern) characters. The Z86C97 currently supports high resolution characters only. A 14-bit PWM port provides enough voltage resolution for a voltage synthesizer tuning system. Seven 6-bit PWM ports are used for controlling audio signal level. Five 8-bit PWM ports are used to vary picture levels. The DTC applications demand powerful I/O capabilities. The Z86C27/C97 fulfills this with 35 I/O pins dedicated to input and output. These lines are grouped into five ports, and are configurable under software control to provide timing, status signals, parallel I/O and an address/data bus for interfacing to external memory. There are three basic address spaces available to support this wide range of configurations: Program Memory, Register File and Data Memory. The Register File is composed of 236 bytes of general purpose register, two I/O Port registers and 15 control and status registers. To unburden the program from coping with the real-time problems such as counting/timing and data communication, the DTC’s offer two on-chip counter/timers with a large number of user selectable modes (see block diagram). Note: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only). DC-2974-04 (6-10-93) 1 Z86C27/C97 CPS DC-2974-04 GENERAL DESCRIPTION (Continued) XTAL1 XTAL2 /RESET RESET Oscillator WDT Counter Timer Counter Timer P30 P31 P34 P35 P36 P40( P10 ) P41( P11 ) P42( P12 ) P43( P13 ) P44( P14 ) P45( P15 ) P46( P16 ) P47( P17 ) P50( P00 ) P51( P01 ) P52( P02 ) P53( P03 ) P54( P04 ) P55( P05 ) P56( P06 ) P57( P07 ) P60( /AS ) P61( /DS ) P62( R//W ) P63( SCLK ) P64( P66 )* P65( P67 )* AFCIN Port 3/ Interrupt 256 Byte Register File PWM 1 14 -bit PWM 1 PWM 2 PWM 3 PWM 4 PWM 5 PWM 6 PWM 7 PWM 8 PWM 9 PWM 10 PWM 11 PWM 12 PWM 13 8K Byte Program ROM Port 2 Z8 CPU Core P27 P26 P25 P24 P23 P22 P21 P20 Port4 (Port 1) Port 0 A8:15 Port 1 AD0:7 PWM 2 to PWM 8 6-bit Port 5 (Port 0) PWM 9 to PWM 13 8-bit 160 Byte Character RAM Port 6 (Control) 4 KByte Character ROM On Screen Display OSCIN OSCOUT HSYNC VSYNC VRED VGREEN VBLUE VBLANK * ( ) Denotes Z86C97 signal differences. Functional Block Diagram 2 Z86C27/C97 CPS DC-2974-04 PIN CONFIGURATION PWM5 PWM4 PWM3 PWM2 PWM1 P35 P36 P34 P31 P30 XTAL1 XTAL2 /RESET P60 GND P61 P62 VCC P63 P64 P65 AFCIN P50 P51 P52 P53 P54 P55 P56 P57 OSCIN OSCOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PWM6 PWM7 PWM8 PWM9 PWM10 PWM11 PWM12 PWM13 P27 P26 P25 P24 P23 GND P22 P21 VCC P20 P47 P46 P45 P44 P43 P42 P41 P40 VBLANK VBLUE VGREEN VRED VSYNC HSYNC PWM5 PWM4 PWM3 PWM2 PWM1 P35 P36 P34 P31 P30 XTAL1 XTAL2 /RESET /AS GND /DS R//W VCC SCLK P66 P67 AFCIN P00 P01 P02 P03 P04 P05 P06 P07 OSCIN OSCOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 .


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