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XR16C2850 Dataheets PDF



Part Number XR16C2850
Manufacturers Exar Corporation
Logo Exar Corporation
Description 2.97V TO 5.5V DUAL UART
Datasheet XR16C2850 DatasheetXR16C2850 Datasheet (PDF)

áç APRIL 2002 XR16C2850 3.3V AND 5V DUART WITH 128-BYTE FIFO REV. 2.0.0 GENERAL DESCRIPTION The XR16C28501 (2850) is an enhanced dual universal asynchronous receiver and transmitter (UART). Enhanced features include 128 bytes of TX and RX FIFOs, programmable TX and RX FIFO trigger level, FIFO level counters, automatic (RTS/CTS) hardware and (Xon/Xoff) software flow control, automatic RS485 half duplex direction control output and data rates up to 6.25 Mbps at 5V and 8X sampling clock. Onboard .

  XR16C2850   XR16C2850


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áç APRIL 2002 XR16C2850 3.3V AND 5V DUART WITH 128-BYTE FIFO REV. 2.0.0 GENERAL DESCRIPTION The XR16C28501 (2850) is an enhanced dual universal asynchronous receiver and transmitter (UART). Enhanced features include 128 bytes of TX and RX FIFOs, programmable TX and RX FIFO trigger level, FIFO level counters, automatic (RTS/CTS) hardware and (Xon/Xoff) software flow control, automatic RS485 half duplex direction control output and data rates up to 6.25 Mbps at 5V and 8X sampling clock. Onboard status registers provide the user with operational status and data error flags. An internal loopback capability allows system diagnostics. The 2850 has a full modem interface and can operate at 3.3 V or 5 V and is pin-to-pin compatible to Exar’s ST16C2550 and XR16C2750 except the 48-TQFP package. The 2850 register set is compatible to the industry standard ST16C2550 and is available in 48pin TQFP , 44-pin PLCC and 40-pin PDIP packages. The 40-pin package does not offer TXRDY# and RXRDY# pins (DMA signal monitoring) otherwise the three package versions are the same. NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,832,205 FEATURES • Pin-to-pin compatible and functionally compatible to Exar’s ST16C2550 and XR16L2750 and TI’s TL16C752B on the 44-PLCC package • Pin-alike Exar’s XR16L2750 and ST16C2550 48TQFP package but with additional CLK8/16, CLKSEL and HDCNTL inputs • Two independent UART channels • Register set compatible to 16C550 • Up to 6.25 Mbps at 5V, and 4 Mbps at 3.3V • Transmit and Receive FIFOs of 128 bytes • Programmable TX and RX FIFO Trigger Levels • Transmit and Receive FIFO Level Counters • Automatic Hardware (RTS/CTS) Flow Control • Selectable Auto RTS Flow Control Hysteresis • Automatic Software (Xon/Xoff) Flow Control • Automatic RS-485 Half-duplex Direction Control Output • Wireless Infrared (IrDA 1.0) Encoder/Decoder • Automatic sleep mode • Full modem interface • Device Identification and Revision • Crystal oscillator or external clock input • Industrial and commercial temperature ranges • 48-TQFP and 44-PLCC packages APPLICATIONS • Portable Appliances • Telecommunication Network Routers • Ethernet Network Routers • Cellular Data Devices • Factory Automation and Process Controls FIGURE 1. XR16C2850 BLOCK DIAGRAM A2:A0 D7:D0 IOR# IOW# CSA# CSB# INTA INTB TXRDYA# TXRDYB# RXRDYA# RXRDYB# HDCNTL# CLKSEL CLK8/16 Reset 8-bit Data Bus Interface UART Channel A UART Regs BRG 128 Byte TX FIFO TX & RX IR ENDEC 3.3V or 5V VCC GND TXA, RXA, DTRA#, DSRA#, RTSA#, DTSA#, CDA#, RIA#, OP2A# 128 Byte RX FIFO TXB, RXB, DTRB#, DSRB#, RTSB#, CTSB#, CDB#, RIB#, OP2B# XTAL1 XTAL2 UART Channel B (same as Channel A) Crystal Osc/Buffer EXAR Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com • [email protected] áç 3.3V AND 5V DUART WITH 128-BYTE FIFO XR16C2850 REV. 2.0.0 FIGURE 2. PIN OUT ASSIGNMENT TXRDYA# 48 VCC 45 43 42 41 40 38 47 46 44 39 37 HDCNTL# DSRA# RIA# D2 D1 D0 CTSA# D4 D3 CDA# D5 D6 D7 RXB RXA TXRDYB# TXA TXB OP2B# 1 2 3 4 5 6 7 8 9 36 35 34 33 RESET DTRB# DTRA# RTSA# OP2A# RXRDYA# INTA INTB A0 A1 A2 CLKSEL XR16C2850 48-pin TQFP 32 31 30 29 28 27 26 25 D0 D1 D2 D3 D4 D5 D6 D7 RXB 1 2 3 4 5 6 7 8 40 39 38 37 36 35 34 33 VCC RIA# CDA# DSRA# CTSA# RESET DTRB# DTRA# RTSA# OP2A# INTA INTB A0 A1 A2 CTSB# RTSB# RIB# DSRB# IOR# CSA# 10 CSB# 11 NC 12 15 13 18 19 20 22 16 14 17 21 23 CTSB# 24 CLK8/16 RXRDYB# DSRB# RTSB# XTAL2 CDB# XTAL1 IOW# IOR# RIB# GND DSRA# CTSA# RXA TXA TXB 39 38 37 36 RESET DTRB# DTRA# RTSA# 10 11 12 13 14 15 16 17 18 19 20 XR16C2850 40-pin PDIP 9 32 31 30 29 28 27 26 25 24 23 22 21 TXRDYA# 44 43 42 CDA# RIA# VCC D4 D3 D2 D1 D0 41 40 6 5 4 3 2 1 D5 D6 D7 RXB RXA TXRDYB# TXA TXB OP2B# CSA# CSB# 7 8 9 10 11 12 13 14 15 16 17 XTAL1 18 XTAL2 19 IOW# 20 CDB# 21 GND 22 RXRDYB# 23 IOR# 24 DSRB# 25 RIB# 26 RTSB# 27 CTSB# 28 OP2B# CSA# CSB# XTAL1 XTAL2 IOW# CDB# GND 35 OP2A# XR16C2850 44-pin PLCC 34 33 32 31 RXRDYA# INTA INTB A0 30 A1 29 A2 ORDERING INFORMATION PART NUMBER (COMMERCIAL) XR16C2850CP40 XR16C2850CJ44 XR16C2850CM48 PACKAGE 40-PDIP 44-PLCC 48-TQFP OPERATING TEMPERATURE RANGE 0°C to +70°C 0°C to +70°C 0°C to +70°C PART NUMBER (INDUSTRIAL) XR16C2850IP40 XR16C2850IJ44 XR16C2850IM48 PACKAGE 40-PDIP 44-PLCC 48-TQFP OPERATING TEMPERATURE RANGE -40°C to +85°C -40°C to +85°C -40°C to +85°C 2 XR16C2850 REV. 2.0.0 3.3V AND 5V DUART WITH 128-BYTE FIFO áç PIN DESCRIPTIONS NAME 40-PDIP PIN # 44-PLCC PIN # 48-TQFP PIN # TYPE DESCRIPTION DATA BUS INTERFACE A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 IOR# 26 27 28 8 7 6 5 4 3 2 1 21 29 30 31 9 8 7 6 5 4 3 2 24 26 27 28 3 2 1 48 47 46 45 44 19 I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction. Data bus lines [7:0] (bidirectional). I/O I Input/Output Read Strobe (active low). The falling edge instigates an internal read cycle and retr.


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