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SCAN92LV090 Dataheets PDF



Part Number SCAN92LV090
Manufacturers National Semiconductor
Logo National Semiconductor
Description 9 Channel Bus LVDS Transceiver with 1149.1 Access
Datasheet SCAN92LV090 DatasheetSCAN92LV090 Datasheet (PDF)

SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN February 2005 SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN General Description The SCAN92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are inte.

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SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN February 2005 SCAN92LV090 9 Channel Bus LVDS Transceiver w/ Boundary SCAN General Description The SCAN92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop back support. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector. The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common mode noise rejection of ± 1V. The receiver threshold is less than ± 100 mV over a ± 1V common mode range and translates the differential Bus LVDS to standard (TTL/CMOS) levels. This device is compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), Test Clock (TCK), and the optional Test Reset (TRST). Features IEEE 1149.1 (JTAG) Compliant Bus LVDS Signaling Low power CMOS design High Signaling Rate Capability (above 100 Mbps) 0.1V to 2.3V Common Mode Range for VID = 200mV ± 100 mV Receiver Sensitivity Supports open and terminated failsafe on port pins 3.3V operation Glitch free power up/down (Driver & Receiver disabled) Light Bus Loading (5 pF typical) per Bus LVDS load Designed for Double Termination Applications Balanced Output Impedance Product offered in 64 pin LQFP package and BGA package n High impedance Bus pins on power off (VCC = 0V) n n n n n n n n n n n n n Simplified Functional Diagram 10124201 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2005 National Semiconductor Corporation DS101242 www.national.com SCAN92LV090 Connection Diagrams 10124202 Top View Order Number SCAN92LV090VEH See NS Package Number VEH064DB 10124216 Top View Order Number SCAN92LV090SLC See NS Package Number SLC64A www.national.com 2 SCAN92LV090 Pinout Description Pin Name DO+/RI+ DO−/RI− DIN RO RE DE GND VCC AGND AVCC TRST TMS TCK TDI TDO TQFP Pin # 27, 31, 35, 37, 41, 45, 47, 51, 55 26, 30, 34, 36, 40, 44, 46, 50, 54 2, 6, 12, 18, 20, 22, 58, 60, 62 3, 7, 13, 19, 21, 23, 59, 61, 63 17 16 4, 5, 9, 14, 25, 56 10, 15, 24, 57, 64 28, 33, 43, 49, 53 29, 32, 42, 48, 52 39 38 1 8 11 BGA Pin # A7, B8, C6, D5, D8, E6, F7, G5, G6 B5, B6, C7, D6, E5, E8, F6, G8, H7 A2, A4, C3, C4, D2, E3, G3, G4, H3 A3, B3, C1, C2, D4, E4, F4, G1, H2 H1 G2 B1, B4, D3, E1, F2, H5 A1, A5, F1, F3, H4 A8, C5, D7, F5, G7 .


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