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SC14425 Dataheets PDF



Part Number SC14425
Manufacturers National Semiconductor
Logo National Semiconductor
Description Complete Baseband processor for DECT Base Stations with Caller-id and Handsfree
Datasheet SC14425 DatasheetSC14425 Datasheet (PDF)

SC14425 Complete Baseband processor for DECT Base Stations PRELIMINARY FEBRUARY 2000 SC14425 Complete Baseband processor for DECT Base Stations with Caller-id and Handsfree General Description The SC14425SC14425 is a 3.3 Volt CMOS IC optimized to handle all the audio, signal and data processing needed within a DECT base station. An ADPCM transcoder, a very low power 14 bit Codec and Analog Frontend are integrated. Direct connections towards analog or ISDN line interface. The SC14425 has an on-.

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SC14425 Complete Baseband processor for DECT Base Stations PRELIMINARY FEBRUARY 2000 SC14425 Complete Baseband processor for DECT Base Stations with Caller-id and Handsfree General Description The SC14425SC14425 is a 3.3 Volt CMOS IC optimized to handle all the audio, signal and data processing needed within a DECT base station. An ADPCM transcoder, a very low power 14 bit Codec and Analog Frontend are integrated. Direct connections towards analog or ISDN line interface. The SC14425 has an on-chip dedicated flexible DSP optimized for telecom applications caller-id, handsfree and allows easy connection to digital telephone answering machine devices. The SC14425 is designed to be compatible with many radio interfaces. A dedicated TDMA controller handles all physical layer slot formats and radio control. The integrated National Semiconductor’s standard CR16B processor core takes care of all the higher protocol stack. Programmable I/O ports can be configured as chip selects for I/O expanders, Serial Flashes, interrupt source or I/O. A digital serial interface can be configured to interface to industry-standard c odecs and ISDN devices with µ-Law, a-Law, linear or transparent data formats. n Embedded flexible dedicated DSP executing Caller-id (CID), Caller-id on Call Waiting (CIDCW) and handsfree, two echo cancellers, two echo suppressors, extended DTMF detection, DTMF generation, sidetone and artificial echo loss. n Two full duplex 32 kbits/sec ADPCM transcoder. n On-chip Dedicated Instruction Processor (DiP) for all TDMA based events, which supports 1.152MHz, 0.576MHz and 0.288MHz data rates. n Protected and unprotected full and double slot B-fields n Standard DECT encryption with different keys for different MAC-connections. n At least 6 MAC connections can be handled simultaneously. n Flexible three wire interface to radio front synthesizer. n One 14-bit linear CODEC with programmable gain n Peak hold ADC for RSSI measurement n Two input 8 bit successive approximation ADC. n Three general purpose I/O ports with programmable interrupts n Full duplex UART, SPI T M and MICROWIRE T M interface. n Flexible 8 kHz synchronous Serial interface to external codecs and ISDN interface circuits. n Two general purpose timers and watch dog timer. n Programmable chip selects to 8 bit wide ROM, SRAM NAND Flash Memory and I/O expanders. n Two Capture timers for frequency measurement for e.g. metering, ringing and call progress tone detection. n 100 pin TQFP-100 package. Note 1: CompactRISCTM is a trademark of National Semiconductor Corporation, SPI T M is a trademark of Motorola. Features n Integrated DECT base band transceiver optimized for GAP base stations according to ETS 300 175-2,3 & 8. n 2.7 to 3.3 Volt operating voltage. n Embedded 16 bit CompactRISCT M CR16B Microprocessor with In System Emulation (ISE) mode. n On-chip 6kByte Data Memory. ________________________________________________________________________________________________ System Diagram sc14404 sc14404 ISDN or Data Interface ISDN sc14425 CID Handsfree PSTN Interface PSTN Interface sc14404 sc14404 sc14404 PSTN1 PSTN2 Copyright 2000 National Semiconductor Corp. 1 www.national.com Order Number SC14425XVJG (Standard version) X=silicon revision See NS Package Number VJG100A Note 1: All digital outputs can sink/source 2 mA unless otherwise specified. All digital inputs are Schmitt trigger types. After reset all I/Os are set to input and all pull-up or pull-down resistors are enabled unless otherwise specified. PU = Pull-up resistor enabled, PD = Pull-down resistor enabled, I = input A-I, B-I = In Boot mode A or B input and pull-up or pull-down resistor disabled, A-PD, B-PU = In Boot mode A, Pull-down resistor enabled. In Boot mode B, pull-up resistor enabled. Note 2: Note 3: Reset state of address and WRn, RDn pins: Hi-Z/1 means Hi-Z if RSTn is LOW, if RSTn goes HIGH is takes 32 SCLK cycles = 25 usec before these pin drives a ‘1’. 5 Volt protection pads: type *P may NOT be connected to an external pull down resistor Copyright 2000 National Semiconductor Corp. 2 ICLK COUT CIN DAC0 ADC0 HOLDACKN ADC1 SC14425 Complete Baseband processor for DECT Base Stations 1.0 CONNECTION DIAGRAM P1[5] AD18 INT5n AD4 AD5 AD6 AD7 AD12 AD15 AD16 WRn AD17 AD14 AD13 AD8 AD9 AD11 RDn AD10 RCSn VSS VDD DAB7 DAB6 DAB5 DAB4 DAB3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 SCLK PD7 PD6 PD5 PD4 PD3 PD2 PD1 VDD VSS RFCLK VDDRF DAC2 DAC Xtal1 CAP AVS AVD RSSI RDI CMPREF TDO MEN1n SO SK SC14425 DAB2 DAB 1 DAB0 AD0 AD1 AD2 AD3 P1[6] ACSn INTn6 P1[7] HOLDn MI INTn7 RSTn AVS2 AVD2 LRS2+ LRS2VREF2MIC2AGND MIC2+ VREF2+ CAP2+ CAP2N.C. N.C. N.C. N.C. UTX URX CS0 CS1 TONE READY CS2 AD19 CLK100 P10_INT INTn0 SCK INTn1 SEN INTn2 SDI INTn3 SDO INTn4 STR0 STR1 PWM P0[0] P0[1] P0[2] P0[3] P0[4] P0[5] P0[6] P0[7.


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