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SL4071B Dataheets PDF



Part Number SL4071B
Manufacturers System Logic Semiconductor
Logo System Logic Semiconductor
Description Quad 2-Input OR Gate
Datasheet SL4071B DatasheetSL4071B Datasheet (PDF)

SL4071B Quad 2-Input OR Gate High-Voltage Silicon-Gate CMOS The SL4071B OR gates provide the system designer wich direct emplementation of the positive-logic OR function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C • Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION SL4071BN Plastic SL4071BD SOIC TA = .

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SL4071B Quad 2-Input OR Gate High-Voltage Silicon-Gate CMOS The SL4071B OR gates provide the system designer wich direct emplementation of the positive-logic OR function. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C • Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION SL4071BN Plastic SL4071BD SOIC TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Inputs PIN 14 =VCC PIN 7 = GND A L L H H B L H L H Output Y L H H H SLS System Logic Semiconductor SL4071B MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN PD PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +20 -0.5 to VCC +0.5 -0.5 to VCC +0.5 ±10 750 500 100 -65 to +150 260 Unit V V V mA mW mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Min 3.0 0 -55 Max 18 VCC +125 Unit V V °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open. SLS System Logic Semiconductor SL4071B DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Minimum Output Low (Sink) Current Test Conditions VOUT=VCC - 0.5V VOUT=VCC - 1.0V VOUT=VCC - 1.5V VOUT=0.5 V or VCC - 0.5 V VOUT=1 V or VCC - 1 V VOUT=1.5 V or VCC - 1.5 V VIN=GND or VCC V 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 18 5.0 10 15 20 5.0 10 15 5.0 5.0 10 15 Guaranteed Limit ≥-55°C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 ±0.1 0.25 0.5 1.0 5.0 0.64 1.6 4.2 -2.0 -0.64 -1.6 -4.2 25°C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 ±0.1 0.25 0.5 1.0 5.0 0.51 1.3 3.4 -1.6 -0.51 -1.3 -3.4 ≤125 °C 3.5 7 11 1.5 3 4 4.95 9.95 14.95 0.05 0.05 0.05 ±1.0 7.5 15 30 150 0.36 0.9 2.4 mA -1.15 -0.36 -0.9 -2.4 Unit V VIL V VOH V VOL VIN=GND V IIN ICC VIN= GND or VCC VIN= GND or VCC µA µA IOL VIN= GND or VCC UOL=0.4 V UOL=0.5 V UOL=1.5 V mA IOH Minimum Output High VIN= GND or VCC (Source) Current UOH=2.5 V UOH=4.6 V UOH=9.5 V UOH=13.5 V SLS System Logic Semiconductor SL4071B AC ELECTRICAL CHARACTERISTICS (CL=50pF, RL=200kΩ , Input t r=t f=20 ns) VCC Symbol tPLH, t PHL Parameter Maximum Propagation Delay, Input A or B to Output Y (Figure 1) Maximum Output Transition Time, Any Output (Figure 1) Maximum Input Capacitance V 5.0 10 15 5.0 10 15 Guaranteed Limit ≥-55°C 250 120 90 200 100 80 25°C 250 120 90 200 100 80 7.5 ≤125°C 500 240 180 400 200 160 Unit ns tTLH, t THL ns CIN pF Figure 1. Switching Waveforms EXPANDED LOGIC DIAGRAM (1/4 of the Device) SLS System Logic Semiconductor .


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