K9K1208U0M-YCB0

K9K1208U0M-YCB0, K9K1208U0M-YIB0 Document Title 64M x 8 Bit NAND Flash Memory Revision History Revision No 0.0 FLASH MEMORY History 1. Initial issue - The followings are disprepancy items between K9K5608U0M (256Mb DDP) and K9K1208U0M (512Mb DDP). AC Characteristics Read Cycle Time (tRC) Write Cycle Time (tWC) WE High hold Time (tWH) Data Hold Time (tDH) RE High Hold Time (tREH) K9K5608U0M Min. 50ns Min. 50ns Min. 15ns Min. 10ns Min. 15ns K9K1208U0M Min. 60ns Min. 60ns Min. 25ns Min. 15ns Min. 25ns Draft Date June 19th 2000 Remark Preliminary 0.1 1. Changed Input / Output Capacitance - Input / Output Capacitance (Max.) : 20 pF --> 30pF - Input Capacitance (Max.) : 20 pF --> 30pF 1. Changed SE pin description - SE is recommended to coupled to GND or Vcc and should not be toggled during reading or programming. 1. Changed don’ t care mode in address cycles - *X can be "High" or "Low" => *L must be set to "Low" 2. Explain how pointer operation works in detail. 3. Renamed GND input (pin # 6) on behalf of SE (pin # 6) - The SE input controls the access of the spare area. When SE is high, the spare area is not accessible for reading or programming. SE is rec ommended to be coupled to GND or Vcc and should not be toggled during reading or programming. => Connect this input pin to GND or set to static low state unless the sequential read mode excluding spare area is used. 4. Updated operation for tRST timing - If reset command(FFh) is written at Ready state, the device goes into ...