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K9F2808U0M-YIB0 Dataheets PDF



Part Number K9F2808U0M-YIB0
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description 16M x 8 Bit NAND Flash Memory
Datasheet K9F2808U0M-YIB0 DatasheetK9F2808U0M-YIB0 Datasheet (PDF)

www.DataSheet4U.com K9F2808U0M-YCB0, K9F2808U0M-YIB0 Document Title 16M x 8 Bit NAND Flash Memory FLASH MEMORY Revision History Revision No. History 0.0 1.0 Initial issue. 1. Changed tPROG Parameter : 1ms(Max.) → 500µs(Max.) 2. Changed tBERS Parameter : 4ms(Max.) → 3ms(Max.) 3. Changed Input and Output Timing Level 0.8V and 2.0V → 1.5V 1. Changed tR Parameter : 7µs(Max.) → 10µ s(Max.) 2. Changed Nop : 10 cycles(Max.) → Main Array 2 cycles(Max.) Spare Array 3 cycles(Max.) t care mode during th.

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www.DataSheet4U.com K9F2808U0M-YCB0, K9F2808U0M-YIB0 Document Title 16M x 8 Bit NAND Flash Memory FLASH MEMORY Revision History Revision No. History 0.0 1.0 Initial issue. 1. Changed tPROG Parameter : 1ms(Max.) → 500µs(Max.) 2. Changed tBERS Parameter : 4ms(Max.) → 3ms(Max.) 3. Changed Input and Output Timing Level 0.8V and 2.0V → 1.5V 1. Changed tR Parameter : 7µs(Max.) → 10µ s(Max.) 2. Changed Nop : 10 cycles(Max.) → Main Array 2 cycles(Max.) Spare Array 3 cycles(Max.) t care mode during the data-loading and reading 3. Added CE don’ 1. Revised real-time map-out algorithm(refer to technical notes) 1. Changed device name - KM29U128T -> K9F2808U0M-YCB0 - KM29U128IT -> K9F2808U0M-YIB0 1. Changed SE pin description - SE is recommended to coupled to GND or Vcc and should not be toggled during reading or programming. Draft Date April 10th 1998 July 14th 1998 Remark Preliminary Final 1.1 April 10th 1999 Final 1.2 1.3 June 30th 1999 Sep. 15th 1999 Final Final 1.4 July 17th 2000 Final Note : For more detailed features and specifications including FAQ, please refer to Samsung’ s Flash web site. http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you. www.DataSheet4U.com 1 www.DataSheet4U.com K9F2808U0M-YCB0, K9F2808U0M-YIB0 16M x 8 Bit NAND Flash Memory FEATURES • Voltage supply : 2.7V~3.6V • Organization - Memory Cell Array : (16M + 512K)bit x 8bit - Data Register : (512 + 16)bit x8bit • Automatic Program and Erase - Page Program : (512 + 16)Byte - Block Erase : (16K + 512)Byte • 528-Byte Page Read Operation - Random Access : 10µ s(Max.) - Serial Page Access : 50ns(Min.) • Fast Write Cycle Time - Program Time : 200µ s(typ.) - Block Erase Time : 2ms(typ.) • Command/Address/Data Multiplexed I/O port • Hardware Data Protection - Program/Erase Lockout During Power Transitions • Reliable CMOS Floating-Gate Technology - Endurance : 1Million Program/Erase Cycles - Data Retention : 10 years • Command Register Operation • Package : 48 - pin TSOP Type1 - 12 x 20 / 0.5 mm pitch FLASH MEMORY GENERAL DESCRIPTION The K9F2808U0M is a 16M(16,777,216)x8bit NAND Flash Memory with a spare 512K(524,288)x8bit. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation programs the 528-byte page in typically 200µs and an erase operation can be performed in typically 2ms on a 16K-byte block. Data in the page can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command inputs. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verify and margining of data. Even the write-intensive systems can take advantage of the K9F2808U0M′s extended reliability of 1,000,000 program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F2808U0M is an optimum solution for large nonvolatile storage applications such as solid state file storage, digital voice recorder, digital still camera and other portable applications requiring non-volatility. PIN CONFIGURATION PIN DESCRIPTION N.C N.C N.C N.C N.C SE R/B RE CE N.C N.C Vcc Vss N.C N.C CLE ALE WE WP N.C N.C N.C N.C N.C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48-pin TSOP1 Standard Type 12mm x 20mm 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C Pin Name I/O0 ~ I/O7 CLE ALE CE RE WE WP SE R/B VCC VSS N.C Pin Function Data Input/Outputs Command Latch Enable Address Latch Enable Chip Enable Read Enable Write Enable Write Protect Spare area Enable Ready/Busy output Power Ground No Connection NOTE : Connect all VCC and V SS pins of each device to common power supply outputs. Do not leave V CC or VSS disconnected. www.DataSheet4U.com 2 www.DataSheet4U.com K9F2808U0M-YCB0, K9F2808U0M-YIB0 Figure 1. FUNCTIONAL BLOCK DIAGRAM VCC VSS A9 - A23 X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Y-Gating FLASH MEMORY 2nd half Page Register & S/A 128M + 4M Bit NAND Flash ARRAY (512 + 16)Byte x 32768 1st half Page Register & S/A A0 - A7 A8 Command Command Register Y-Gating I/O Buffers & Latches VCC VSS I/0 0 I/0 7 CE RE WE Control Logic & High Voltage Generator Global Buffers Output Driver CLE ALE WP Figure 2. ARRAY ORGANIZATION 1 Block = 32 Row (16K + 512) Bytes 32K Pages (=1024 Blocks) 1st half Page Register (=256 Bytes) 2nd half Page Register (=256 Bytes) 1 Page = 528 Bytes 1 Block = 528 B x 32 Pages = (16K + 512) Bytes 1 Device = 528B x 32Pages x 1024 Blo.


K9F2808U0M-YCB0 K9F2808U0M-YIB0 K9F2816Q0C-DCB0


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