K7R321882M

K7R323682M K7R321882M K7R320982M Document Title 1Mx36 & 2Mx18 & 4Mx9 QDR TM II b2 SRAM 1Mx36-bit, 2Mx18-bit, 4Mx9-bit QDRTM II b2 SRAM Revision History Rev. No. 0.0 0.1 History 1. Initial document. 1. 2. 3. 4. 5. 6. Pin name change from DLL to Doff. Vddq range change from 1.5V to 1.5V~1.8V. Update JTAG test conditions. Reserved pin for high density name change from NC to Vss/SA Delete AC test condition about Clock Input timing Reference Level Delete clock description on page 2 and add HSTL I/O comment Draft Date June, 30 2001 Dec. 5 2001 Remark Advance Preliminary 0.2 1. Update current characteristics in DC electrical characteristics 2. Change AC timing characteristics 3. Update JTAG instruction coding and diagrams 1. 2. 3. 4. 5. 1. 2. 3. 4. Add 4Mx9 Organization. Add -FC25 part (Part Number, Idd, AC Characteristics) Add AC electrical characteristics. Change AC timing characteristics. Change DC electrical characteristics(ISB1) Change the data Setup/Hold time. Change the Access Time.(tCHQV, tCHQX, etc.) Change the Clock Cycle Time.(MAX value of tKHKH) Change the JTAG instruction coding. July, 29. 2002 Preliminary 0.3 Sep. 6. 2002 Preliminary 0.4 Oct. 7. 2002 Preliminary 0.5 1. Change the Boundary scan exit order. 2. Change the AC timing characteristics(-25, -20) 3. Correct the Overshoot and Undershoot timing diagrams. 1. Change the JTAG Block diagram 1. Correct the JTAG ID register definition 2. Correct the AC timing parameter (delete the tKHKH Max value) 3. Cha...