16Mx16 SDRAM 54CSP
K4S561633C-R(B)L/N/P
CMOS SDRAM
16Mx16 SDRAM 54CSP
(VDD/VDDQ 3.0V/3.0V or 3.3V/3.3V)
Revision 1.4 December 2002
Rev....
Description
K4S561633C-R(B)L/N/P
CMOS SDRAM
16Mx16 SDRAM 54CSP
(VDD/VDDQ 3.0V/3.0V or 3.3V/3.3V)
Revision 1.4 December 2002
Rev. 1.4 Dec. 2002
K4S561633C-R(B)L/N/P
4M x 16Bit x 4 Banks Synchronous DRAM in 54CSP
FEATURES
3.0V & 3.3V power supply. LVCMOS compatible with multiplexed address. Four banks operation. MRS cycle with address key programs. -. CAS latency (1 & 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). All inputs are sampled at the positive going edge of the system clock. Burst read single-bit write operation. DQM for masking Auto refresh. 64ms refresh period (8K cycle). Commercial Temperature Operation (-25° C ~ 70 °C). Extended Temperature Operation ( -25° C ~ 85 °C). Inderstrial Temperature Operation ( -40° C ~ 85° C). 54balls CSP (-RXXX - Pb, -BXXX - Pb Free)
CMOS SDRAM
GENERAL DESCRIPTION
The K4S561633C is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Part No. K4S561633C-R(B)L/N/P75 K4S561633C-R(B)L/N/P1H K4S561633C-R(B)L/N/P1L Max Freq. 133M...
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