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K4S281632C-TI1H Dataheets PDF



Part Number K4S281632C-TI1H
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
Datasheet K4S281632C-TI1H DatasheetK4S281632C-TI1H Datasheet (PDF)

K4S281632C-TI(P) CMOS SDRAM 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.1 June 2001 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.1 Jun. 2001 K4S281632C-TI(P) Revision History Revision 0.0 (November 18, 2000) • First generation. CMOS SDRAM Revision 0.1 (June 20, 2001) • Final Specification. Rev. 0.1 Jun. 2001 K4S281632C-TI(P) 2M x 16Bit x 4 Banks Synchronous DRAM FEATURES • JEDEC standard 3.3V power supply •.

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K4S281632C-TI(P) CMOS SDRAM 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.1 June 2001 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.1 Jun. 2001 K4S281632C-TI(P) Revision History Revision 0.0 (November 18, 2000) • First generation. CMOS SDRAM Revision 0.1 (June 20, 2001) • Final Specification. Rev. 0.1 Jun. 2001 K4S281632C-TI(P) 2M x 16Bit x 4 Banks Synchronous DRAM FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation • DQM for masking • Auto & self refresh • 64ms refresh period (4K cycle) • Industrial Temperature Operation (- 40 to 85 °C) CMOS SDRAM GENERAL DESCRIPTION The K4S281632C is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Part No. K4S281632C-TI/P75 K4S281632C-TI/P1H K4S281632C-TI/P1L Max Freq. 133MHz(CL=3) 100MHz(CL=2) 100MHz(CL=3) LVTTL Interface Package 54 TSOP(II) FUNCTIONAL BLOCK DIAGRAM I/O Control LWE Data Input Register LDQM Bank Select 2M x 16 2M x 16 2M x 16 2M x 16 Refresh Counter Output Buffer Row Decoder Sense AMP Row Buffer DQi Address Register CLK ADD Column Decoder Col. Buffer LRAS LCBR Latency & Burst Length LCKE LRAS LCBR LWE LCAS Programming Register LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE LDQM UDQM * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.1 Jun. 2001 K4S281632C-TI(P) PIN CONFIGURATION (Top view) V DD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 V DD LDQM WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 V DD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 V SS DQ15 V SSQ DQ14 DQ13 V DDQ DQ12 DQ11 V SSQ DQ10 DQ9 V DDQ DQ8 V SS N.C/RFU UDQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 V SS CMOS SDRAM 54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch) PIN FUNCTION DESCRIPTION Pin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multiplexed on the same pins. Row address : RA 0 ~ RA 11, Column address : CA0 ~ CA 8 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. CKE Clock enable A 0 ~ A11 BA 0 ~ BA1 RAS CAS WE L(U)DQM DQ0 ~ 15 V D D/V SS V DDQ /V SSQ N.C/RFU Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground Data output power/ground No connection /reserved for future use Rev. 0.1 Jun. 2001 K4S281632C-TI(P) ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VI N, V OUT V DD , VDDQ TS T G PD I OS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50 CMOS SDRAM Unit V V °C W mA Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high.


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