Document
IS89C52
IS89C52
CMOS SINGLE CHIP 8-BIT MICROCONTROLLER with 8-Kbytes of FLASH
ISSI
NOVEMBER 1998 GENERAL DESCRIPTION
ISSI®
®
FEATURES
• 80C51 based architecture • 8-Kbytes of on-chip Reprogrammable Flash Memory • 256 x 8 RAM • Three 16-bit Timer/Counters • Full duplex serial channel • Boolean processor • Four 8-bit I/O ports, 32 I/O lines • Memory addressing capability – 64K ROM and 64K RAM • Program memory lock – Lock bits (3) • Power save modes: – Idle and power-down • Eight interrupt sources • Most instructions execute in 0.3 µs • CMOS and TTL compatible • Maximum speed: 40 MHz @ Vcc = 5V • Industrial temperature available • Packages available: – 40-pin DIP – 44-pin PLCC – 44-pin PQFP
The ISSI IS89C52 is a high-performance microcontroller fabricated using high-density CMOS technology. The CMOS IS89C52 is functionally compatible with the industry standard 80C51 microcontrollers. The IS89C52 is designed with 8-Kbytes of Flash memory, 258 x 8 RAM; 32 programmable I/O lines; a serial I/O port for either multiprocessor communications, I/O expansion or full duplex UART; three 16-bit timer/counters; an eight-source, two-priority-level, nested interrupt structure; and an on-chip oscillator and clock circuit. The IS89C52 can be expanded using standard TTL compatible memory.
T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8
Figure 1. IS89C52 Pin Configuration: 40-pin PDIP
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
MC013-1C 11/21/98
1
IS89C52
ISSI
P1.1/T2EX P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3
®
P1.0/T2
INDEX P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 7 8 9 10 11 12 13 14 15 16 17
6
5
4
3
2
1
44
VCC
P1.4
P1.3
P1.2
NC
43
42
41
40 39 38 37 36 35 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP NC ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13
TOP VIEW
34 33 32 31 30 29
18
19
20
21
22
23
24
25
26
27
28
A8/P2.0
A9/P2.1
A10/P2.2
A11/P2.3
Figure 2. IS89C52 Pin Configuration: 44-pin PLCC
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
MC013-1C 11/21/98
A12/P2.4
WR/P3.6
RD/P3.7
XTAL2
XTAL1
GND
NC
IS89C52
ISSI
P1.1/T2EX P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3
®
P1.0/T2
P1.4
P1.3
P1.2
44 P1.5 P1.6 P1.7 RST RxD/P3.0 NC TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 1 2 3 4 5 6 7 8 9 10 11 12
43
42
41
40
39
VCC
38
NC
37
36
35
34 33 32 31 30 29 29 27 26 25 24 23 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA NC ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13
13
14
15
16
17
18
19
20
21
22
A10/P2.2
A11/P2.3
Figure 3. IS89C52 Pin Configuration: 44-pin PQFP
Integrated Silicon Solution, Inc. — 1-800-379-4774
MC013-1C 11/21/98
A12/P2.4
WR/P3.6
RD/P3.7
XTAL2
XTAL1
A8/P2.0
A9/P2.1
GND
NC
3
IS89C52
ISSI
P2.0-P2.7 P0.0-P0.7
®
Vcc
P2 DRIVERS
P0 DRIVERS
GND ADDRESS DECODER & 256 BYTES RAM ADDRESS DECODER & 8K FLASH 3 LOCK BITS & 32 BYTES ENCRYPTION
RAM ADDR REGISTER
P2 LATCH
P0 LATCH
B REGISTER
STACK POINT
ACC
PROGRAM ADDRESS REGISTER
PCON SCON T2CON TH0 TL1 TH2 RCAP2L SBUF
TMOD TCON TL0 TH1 TL2 RCAP2H IE IP
TMP2
TMP1
PROGRAM COUNTER
INTERRUPT BLOCK SERIAL PORT BLOCK TIMER BLOCK
ALU
PC INCREMENTER
PSW BUFFER
PSEN ALE/PROG RST EA/VPP TIMING AND CONTROL
INSTRUCTION REGISTER
DPTR
P3 LATCH OSCILLATOR XTAL1 XTAL2 P3 DRIVERS
P1 LATCH
P1 DRIVERS
P3.0-P3.7
P1.0-P1.7
Figure 4. IS89C52 Block Diagram
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
MC013-1C 11/21/98
IS89C52
Table 1. Detailed Pin Description Symbol ALE/PROG PDIP 30 PLCC 33 PQFP 27 I/O I/O Name and Function
ISSI
®
EA/VPP
Address Latch Enable: Output pulse for latching the low byte of the address during an address to the external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the Program Pulse input (PROG) during Flash programming.
31
35
29
I
External Access enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to FFFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 0FFFH. This also receives the 12V programming enable voltage (VPP) during Flash programming. Por.