Document
IS24C32-2/3 IS24C64-2/3
65,536-bit/32,768-bit 2-WIRE SERIAL CMOS EEPROM
FEATURES
• Low Power CMOS Technology – Standby Current less than 10 µA (5.5V) – Read Current (typical) less than 1 mA (5.5V) – Write Current (typical) less than 3 mA (5.5V) • Low Voltage Operation – IS24C64-2 & IS24C32-2: Vcc = 1.8V to 5.5V – IS24C64-3 & IS24C32-3: Vcc = 2.5V to 5.5V • 100 KHz (1.8V) and 400 KHz (5V) Compatibility • Hardware Data Protection – Write Protect Pin • Sequential Read Feature • Filtered Inputs for Noise Suppression
ISSI
• 8-pin PDIP and 8-pin SOIC packages • Self time write cycle with auto clear – 5 ms @ 2.5V • Organization: – IS24C64-2 and IS24C64-3: 8192x8 – IS24C32-2 and IS24C32-3: 4096x8 • 32-Byte Page Write Buffer • Two-Wire Serial Interface – Bi-directional data transfer protocol • High Reliability – Endurance: 1,000,000 Cycles – Data Retention: 100 Years • Commercial and Industrial temperature ranges
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PRELIMINARY INFORMATION APRIL 2001
PRODUCT OFFERING OVERVIEW
Part No IS24C64-2 IS24C64-3 IS24C32-2 IS24C32-3 Voltage 1.8V-5.5V 2.5V-5.5V 1.8V-5.5V 2.5V-5.5V Speed 100 KHz 400 KHz 100 KHz 400 KHz Standby ICC < 5 µA < 10 µA < 5 µA < 10 µA Read ICC 1 mA 1 mA 1 mA 1 mA Write ICC 3 mA 3 mA 3 mA 3 mA Temperature C,I C,I C,I C,I
DESCRIPTION
The IS24C64-2 is a 1.8V (1.8V-5.5V) 64K-bit (8192 x 8) Electrically Erasable PROM, IS24C64-3 is a 2.5V (2.5V5.5V) 64K-bit (8192 x 8) Electrically Erasable PROM, IS24C32-2 is a 1.8V (1.8V-5.5V) 32K-bit (4096 x 8) Electrically Erasable PROM and the IS24C32-3 is a 2.5V (2.5V-5.5V) 32K-bit (4096 x 8) Electrically Erasable PROM. The IS24CXX (IS24C64-2, IS24C64-3, IS24C32-2 and IS24C32-3) family is a low-cost and low voltage 2-wire Serial EEPROM. It is fabricated using ISSI’s advanced CMOS EEPROM technology and provides a low power and low voltage operation. The IS24CXX family features a write protection feature, and is available in 8-pin DIP and 8-pin SOIC packages.
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY INFORMATION 04/04/01 Rev. 00B
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IS24C32-2/3 IS24C64-2/3
FUNCTIONAL BLOCK DIAGRAM
ISSI
HIGH VOLTAGE GENERATOR, TIMING & CONTROL
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Vcc
8
SDA SCL WP
5
7
X DECODER
6
CONTROL LOGIC SLAVE ADDRESS REGISTER & COMPARATOR WORD ADDRESS COUNTER
EEPROM ARRAY
Y DECODER
GND
4
ACK
Clock DI/O
>
nMOS
DATA REGISTER
PIN DESCRIPTIONS
A0-A2 SDA SCL WP Vcc GND Address Inputs Serial Address/Data I/O Serial Clock Input Write Protect Input Power Supply Ground
PIN CONFIGURATION 8-Pin DIP and SOIC
A0 A1 A2 GND
1 2 3 4
8 7 6 5
VCC WP SCL SDA
SCL
This input clock pin is used to synchronize the data transfer to and from the device.
SDA
The SDA is a Bi-directional .