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S5T8554B Dataheets PDF



Part Number S5T8554B
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description 1 CHIP CODEC
Datasheet S5T8554B DatasheetS5T8554B Datasheet (PDF)

1 CHIP CODEC S5T8554B/7B INTRODUCTION 16-CERDIP The S5T8554B/7B are single-chip PCM encoders and decoders (PCM CODECs) and PCM line filters. These devices provide all the functions required to interface a full-duplex voice telephone circuit with a time-division-multiplex (TDM) system. These devices are designed to perform the transmit encoding and receive decoding as well as the transmit and receive filtering functions in PCM system. They are intended to be used at the analog termination of a .

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1 CHIP CODEC S5T8554B/7B INTRODUCTION 16-CERDIP The S5T8554B/7B are single-chip PCM encoders and decoders (PCM CODECs) and PCM line filters. These devices provide all the functions required to interface a full-duplex voice telephone circuit with a time-division-multiplex (TDM) system. These devices are designed to perform the transmit encoding and receive decoding as well as the transmit and receive filtering functions in PCM system. They are intended to be used at the analog termination of a PCM line or trunk. These devices provide the bandpass filtering of the analog signals prior to encoding and after decoding. These combination devices perform the encoding and decoding of voice and call progress tones as well as the signalling and supervision information. 16-DIP-300A 8−DIP−300 FEATURES • • • • • • • Complete CODEC and filtering system Meets or exceeds AT&T D3/D4 and CCITT specifications µ-Law: S5T8554B, A-Law: S5T8557B On-chip auto zero, sample and hold, and precision voltage references Low power dissipation: 60mW (operating), 3mW (standby) ± 5V operation TTL or CMOS compatible Automatic power down ORDERING INFORMATION Device S5T8554B02-L0B0 S5T8557B02-L0B0 S5T8554B01-D0B0 S5T8557B01-D0B0 S5T8554B01-S0B0 S5T8557B01-S0B0 Package 16-CERDIP 16-DIP-300A 16-SOP-BD300 Operating Temperature −25°C to 125°C −25°C to +70°C −25°C to +70°C 1 S5T8554B/7B 1 CHIP CODEC PIN CONFIGURATION V BB GNDA VFRO V CC FSR DR BCLKR/CLKSEL MCLKR/PDN 1 2 3 4 5 6 7 8 16 VFXI+ 15 VFXI14 GSX 13 TSX 12 FSXS 11 DX 10 BCLKX 9 MCLK X S5T8554B/7B KT8554/7 PIN DISCRIPTION Pin No 1 2 3 4 5 6 7 Symbol VBB GNDA VFRO VCC FSR DR BLCKR/ CLKSEL MCLKR/ PDN MCLKX BLCKX DX FSX TSX GSX VFXI − Description VBB = −5V ± 5% Analog ground. Analog output of the receive power Amp. VCC = +5 V ± 5% Receive frame sync pulse. 8kHz pulse train PCM data input. Logic input which selects either 1.536MHz/1.544MHz or 2.048MHz for master clock in normal operation and BCLKX is used for both TX and RX directions. Alternately direct clock input available, vary from 60kHz to 2.048MHz. When MCLK R is connected continuously high, the device is powered down. Normally connected continuously low, MCLKX is selected for all DAC timing. Alternately direct 1.536MHz/1.544MHz or 2.048MHz clock input available. Must be 1.536MHz/1.544MHz or 2.048MHz. May be vary from 64kHz to 2.048MHz but BCLKX is externally tied with MCLKX in normal operation. PCM data output. TX frame sync pulse. 8kHz pulse train. Changed from high to low during the encoder timeslot. Open drain output. Analog output of the TX input amplifier. Used to set gain through external resistor. Inverting input stage of the TX analog signal. Non-inverting input stage of the TX analog signal. 8 9 10 11 12 13 14 15 16 VFXI+ 2 1 CHIP CODEC S5T8554B/7B ABSOLUTE MAXIMUM RATING Characteristic Positive Supply Voltage Negative Supply Voltage Voltage at Any Analog Input or Output Voltage at Any Digital Input or Output Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 secs) Symbol VCC VBB VI (A) VI (D) Ta TSTG TLEAD Value 7 −7 VCC + 0.3 ~ VBB - 0.3 VCC + 0.3 ~ GNDA - 0.3 −25 ~ +125 −65 ~ +150 300 Unit V V V V °C °C °C ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VCC = 5.0V ± 5%, VBB = −5.0V ± 5%, GNDA = 0V, Ta = 0°C to 70°C; typical characteristics specified at VCC = 5.0V, VBB = −5.0V, Ta=25°C; all signals referenced to GNDA) Characteristic POWER DISSIPATION Power-Down Current Power-Down Current Active Current Active Current DIGITAL INTERFACE Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage VIL VIH IIL IIH VOL − − GNDA≤ VIN ≤ VIL, all digital input VIH ≤ VIN ≤ VCC DX, IL = 3.2mA SIGR, IL = 1.0mA TSX, IL = 3.2mA, open drain DX, IH = −3.2mA SIGR, IH = −1.0mA DX, GNDA ≤ VO ≤ VCC − 2.2 −10 −10 − − − − − − 0.6 − 10 10 0.4 0.4 0.4 − 10 V V µA µA V V V V V µA ICC (DOWN) No Load IBB (DOWN) No Load ICC (A) IBB (A) No Load No Load − − − − 0.5 0.05 6.0 6.0 1.5 0.3 9.0 9.0 mA mA mA mA Symbol Test Conditions Min. Typ. Max. Unit Output High Voltage Output Current in High Impedance State (Tri -state) IO (HZ) IO (HZ) 2.4 2.4 −10 − − ANALOG INTERFACE WITH RECEIVE FILTER Output Resistance RO Pin VFRO − 1 3 Ω 3 S5T8554B/7B 1 CHIP CODEC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VCC = 5.0V ± 5%, VBB = −5.0V ± 5%, GNDA = 0V, Ta = 0°C to 70°C; typical characteristics specified at VCC = 5.0V, VBB = −5.0V, Ta=25°C; all signals referenced to GNDA) Characteristic Load Resistance Load Capacitance Output DC Offset Voltage Symbol RL CL VOO (RX) Test Conditions VFRO = ± 2.5V − − -2.5V≤V≤+2.5V, VFXI+ or VFXI-2.5V≤V≤+2.5V, VFXI+ or VFXIClosed loop, unity gain GSX GSX GSX, RL≤10KW VFXI+ to GSX − − CMRRXA > 60dB DC Test DC Test Min. 600 − −200 −200 10 − 10 − ± 2.8 5,000 1 −20 −2.5 60 60 Typ. − − − − − 1 − − − − 2 − − − − Max. − 500 200 Unit Ω pF mV ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER Input Leakage Current Input Resistance Output Res.


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