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S3C72N2 Dataheets PDF



Part Number S3C72N2
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description The S3C72N2/C72N4 single-chip CMOS microcontroller has been designed for high performance using Samsungs newest 4-bit CPU core/ SAM47 (Samsung Arrange
Datasheet S3C72N2 DatasheetS3C72N2 Datasheet (PDF)

S3C72N2/C72N4/P72N4 PRODUCT OVERVIEW 1 OVERVIEW PRODUCT OVERVIEW The S3C72N2/C72N4 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). With features such as, LCD direct drive capability, 8-bit timer/counter, and watch timer, the S3C72N2/C72N4 offers an excellent design solution for a wide variety of applications that require LCD functions. Up to 16 pins of the 64-pin QFP package, it can b.

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S3C72N2/C72N4/P72N4 PRODUCT OVERVIEW 1 OVERVIEW PRODUCT OVERVIEW The S3C72N2/C72N4 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). With features such as, LCD direct drive capability, 8-bit timer/counter, and watch timer, the S3C72N2/C72N4 offers an excellent design solution for a wide variety of applications that require LCD functions. Up to 16 pins of the 64-pin QFP package, it can be dedicated to I/O. Four vectored interrupts provide fast response to internal and external events. In addition, the S3C72N2/C72N4 's advanced CMOS technology provides for low power consumption and a wide operating voltage range. OTP The S3C72N2/C72N4 microcontroller is also available in OTP (One Time Programmable) version, S3P72N4 . The S3P72N4 microcontroller has an on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM. The S3P72N4 is comparable to S3C72N2/C72N4, both in function and in pin configuration. 1-1 PRODUCT OVERVIEW S3C72N2/C72N4/P72N4 FEATURES Memory — 288 × 4-bit RAM — 2048 × 8-bit ROM (S3C72N2) — 4096 × 8-bit ROM (S3C72N4) I/O Pins — Input only: 4 pins — I/O: 12 pins — Output: 8 pins sharing with segment driver outputs LCD Controller/Driver — Maximum 16-digit LCD direct drive capability — 32 segment, 4 common pins — Display modes: Static, 1/2 duty (1/2 bias) 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) 8-Bit Basic Timer — Programmable interval timer — Watchdog timer 8-Bit Timer/Counter — Programmable 8-bit timer — External event counter — Arbitrary clock frequency output Watch Timer — Real-time and interval time measurement — Four frequency outputs to BUZ pin — Clock source generation for LCD Bit Sequential Carrier — Support 16-bit serial data transfer in arbitrary format Package Type — 64-pin QFP Oscillation Sources — Crystal, ceramic, or RC for main system clock — Crystal or external oscillator for subsystem clock — Main system clock frequency: 4.19 MHz (typical) — Subsystem clock frequency: 32.768 kHz — CPU clock divider circuit (by 4, 8, or 64) Instruction Execution Times — 0.95, 1.91, 15.3 µs at 4.19 MHz (main) — 122 µs at 32.768 kHz (subsystem) Operating Temperature — – 40 °C to 85 °C Operating Voltage Range — 2.0 V to 5.5 V at 4.19 MHz — 1.8 V to 5.5 V at 3 MHz Interrupts — Two internal vectored interrupts — Two external vectored interrupts — Two quasi-interrupts Memory-Mapped I/O Structure — Data memory bank 15 Two Power-Down Modes — Idle mode (only CPU clock stops) — Stop mode (main or sub system oscillation stops) 1-2 S3C72N2/C72N4/P72N4 PRODUCT OVERVIEW BLOCK DIAGRAM Watchdog Timer INT0, INT1, INT2 RESET Basic Timer Watch Timer P2.3/BUZ Xin Xout XTin XTout P1.3/TCL0 P2.0/TCLO0 8-Bit Timer/ Counter0 Interrupt Control Block Interrupt Control Block Instruction Register LCD Driver/ Controller P6.0-P6.3/ KS0-KS3 Internal Interrupts I/O Port 6 Program Counter Program Status Word Stack Pointer BIAS VLC0-VLC2 LCDCK/P3.0 LCDSY/P3.1 COM0-COM3 SEG0-SEG23 P8.0-P8.7/ SEG24-SEG31 P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/TCL0 P2.0/TCLO0 P2.1 P2.2/CLO P2.3/BUZ P3.0/LCDCK P3.1/LCDSY P3.2 P3.3 Instruction Decoder Arithmetic and Logic Unit Input Port 1 P8.0-P8.7 SEG24-SEG31 Output Port 8 I/O Port 2 288 x 4-Bit Data Memory 2/4 KByte Program Memory I/O Port 3 Figure 1-1. S3C72N2/C72N4 Simplified Block Diagram 1-3 PRODUCT OVERVIEW S3C72N2/C72N4/P72N4 PIN ASSIGNMENTS 64 63 62 61 60 59 58 57 56 55 54 53 52 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 COM0 COM1 COM2 COM3 BIAS VLC0 VLC1 VLC2 VDD VSS Xout Xin TEST XTin XTout RESET P1.0/INT0 P1.1/INT1 P1.2/INT2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 S3C72N2 S3C72N4 (Top View) 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24/P8.0 SEG25/P8.1 SEG26/P8.2 SEG27/P8.3 SEG28/P8.4 SEG29/P8.5 SEG30/P8.6 SEG31/P8.7 Figure 1-2. S3C72N2/C72N4 64-QFP Pin Assignment 1-4 P1.3/TCL0 P2.0/TCLO0 P2.1 P2.2/CLO P2.3/BUZ P3.0/LCDCK P3.1/LCDSY P3.2 P3.3 P6.0/KS0 P6.1/KS1 P6.2/KS2 P6.3/KS3 20 21 22 23 24 25 26 27 28 29 30 31 32 S3C72N2/C72N4/P72N4 PRODUCT OVERVIEW PIN DESCRIPTIONS Table 1-1. S3C72N2/C72N4 Pin Descriptions Pin Name P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3 Pin Type I Description 4-bit input port. 1-bit or 4-bit read and test is possible. 4-bit pull-up resistors are software assignable. 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable. 4-bit I/O port. 1-bit and 4-bit read/write and test is possible. Each individual pin can be specified as input or output. 4-bit pull-up resistors are software assignable. 4-bit I/O ports. Pins are individually software configurable as input or output. 1-bit and 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable. Output port for 1-bit data (for use as CMOS driver.


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