IDT71V67602

256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Pipelined Outputs, Single Cycle Deselect x x IDT71V67602 IDT71V67802 Features 256K x 36, 512K x 18 memory configurations Supports high system speed: – 166MHz 3.5ns clock access time – 150MHz 3.8ns clock access time – 133MHz 4.2ns clock access time LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 2.5V I/O supply (VDDQ) Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array. Description The IDT71V67602/7802 are high-speed SRAMs organized as 256K x 36/512K x 18. The IDT71V676/78 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the IDT71V67602/7802 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operation is selected (ADV=LOW), the subsequent three cycles of output data wil...