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IN74AC74 Dataheets PDF



Part Number IN74AC74
Manufacturers ETC
Logo ETC
Description Dual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS
Datasheet IN74AC74 DatasheetIN74AC74 Datasheet (PDF)

TECHNICAL DATA IN74AC74 Dual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74AC74 is identical in pinout to the LS/ALS74, HC/HCT74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. This device consists of two D flip-flops with individual Set, Reset, and Clock inputs. Information at a D-input is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q.

  IN74AC74   IN74AC74


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TECHNICAL DATA IN74AC74 Dual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS The IN74AC74 is identical in pinout to the LS/ALS74, HC/HCT74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. This device consists of two D flip-flops with individual Set, Reset, and Clock inputs. Information at a D-input is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q outputs are available from each flip-flop. The Set and Reset inputs are asynchronous. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA; 0.1 µA @ 25°C • High Noise Immunity Characteristic of CMOS Devices • Outputs Source/Sink 24 mA ORDERING INFORMATION IN74AC74N Plastic IN74AC74D SOIC TA = -40° to 85° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Set L H L H H H H PIN 14 =VCC PIN 7 = GND Reset H L L H H H H L H Clock X X X Data X X X H L X X Outputs Q H L H * Q L H H* L H H L No Change No Change H H X No Change *Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously. X = don’t care 99 IN74AC74 MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 ±20 ±50 ±50 750 500 -65 to +150 260 Unit V V V mA mA mA mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TJ TA IOH IOL tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Junction Temperature (PDIP) Operating Temperature, All Package Types Output Current - High Output Current - Low Input Rise and Fall Time (except Schmitt Inputs) * Min 2.0 0 -40 Max 6.0 VCC 140 +85 -24 24 Unit V V °C °C mA mA ns/V VCC =3.0 V VCC =4.5 V VCC =5.5 V 0 0 0 150 40 25 * VIN from 30% to 70% VCC This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 100 IN74AC74 DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low Level Input Voltage Minimum High-Level Output Voltage Test Conditions VOUT=0.1 V or VCC-0.1 V V 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 5.5 5.5 5.5 5.5 4.0 Guaranteed Limits 25 °C 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 ±0.1 -40°C to 85°C 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 ±1.0 75 -75 40 µA mA mA µA V Unit V VIL VOUT=0.1 V or VCC-0.1 V V VOH IOUT ≤ -50 µA V * VIN=VIH or VIL IOH=-12 mA IOH=-24 mA IOH=-24 mA VOL Maximum Low-Level Output Voltage IOUT ≤ 50 µA VIN=VIH or VIL IOL=12 mA IOL=24 mA IOL=24 mA IIN IOLD IOHD ICC Maximum Input Leakage Current +Minimum Dynamic Output Current +Minimum Dynamic Output Current Maximum Quiescent Supply Current (per Package) VIN=VCC or GND VOLD=1.65 V Max VOHD=3.85 V Min VIN=VCC or GND * All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time. Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC * 101 IN74AC74 AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=3.0 ns) VCC* Symbol Parameter V Guaranteed Limits 25 °C Min fmax tPLH tPHL tPLH tPHL CIN Clock Frequency (Figure 1) Propagation Delay, Clock to Q or Q (Figure 1) Propagation Delay, Clock to Q or Q (Figure 1) Propagation Delay, Set or Reset to Q or Q (Figure 2) Propagation Delay, Set or Reset to Q or Q (Figure 2) Maximum Input Capacitance 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 5.0 100 140 4.5 3.5 3.5 2.5 5.0 3.5 4.0 3.0 4.5 13.5 10.0 14.0 10.0 12.5 9.0 12.0 9.5 Max -40°C to 85°C Min 95 125 4.0 3.0 3.5 2.5 4.0 3.0 3.5 2.5 4.5 16.0 10.5 14.5 10.5 13.0 10.0 13.5 10.5 Max MHz ns ns ns ns pF Unit .


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