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ISPPAC10 Dataheets PDF



Part Number ISPPAC10
Manufacturers Lattice Semiconductor
Logo Lattice Semiconductor
Description In-System Programmable Analog Circuit
Datasheet ISPPAC10 DatasheetISPPAC10 Datasheet (PDF)

ispPAC 10 ® In-System Programmable Analog Circuit Features • IN-SYSTEM PROGRAMMABLE (ISP™) ANALOG CIRCUIT — Four Instrument Amplifier Gain/Attenuation Stages — Signal Summation (Up to 4 Inputs) — Precision Active Filtering (10kHz to 100kHz) — No External Components Needed for Configuration — Non-Volatile E2CMOS® Cells (10,000 Cycles) — IEEE 1149.1 JTAG Serial Port Programming • FOUR LINEAR ELEMENT BUILDING BLOCKS — Programmable Gain Range (0dB to 80dB) — Bandwidth of 550kHz (G=1), 330kHz (G=10).

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ispPAC 10 ® In-System Programmable Analog Circuit Features • IN-SYSTEM PROGRAMMABLE (ISP™) ANALOG CIRCUIT — Four Instrument Amplifier Gain/Attenuation Stages — Signal Summation (Up to 4 Inputs) — Precision Active Filtering (10kHz to 100kHz) — No External Components Needed for Configuration — Non-Volatile E2CMOS® Cells (10,000 Cycles) — IEEE 1149.1 JTAG Serial Port Programming • FOUR LINEAR ELEMENT BUILDING BLOCKS — Programmable Gain Range (0dB to 80dB) — Bandwidth of 550kHz (G=1), 330kHz (G=10) — Low Distortion (THD < -74dB max @ 10kHz) — Auto-Calibrated Input Offset Voltage • TRUE DIFFERENTIAL I/O (±3V RANGE) — High CMR (69dB) Instrument Amplifier Inputs — 2.5V Common Mode Reference on Chip — Four Rail-to-Rail Voltage Outputs • 28-PIN PLASTIC DIP OR SOIC PACKAGE — Single Supply 5V Operation • APPLICATIONS INCLUDE INTEGRATED: — Single +5V Supply Signal Conditioning — Active Filters, Gain Stages, Summing Blocks — Analog Front Ends, 12-Bit Data Acq. Systems — Sensor Signal Conditioning Functional Block Diagram OUT2+ OUT2– IN2+ IN2– TDI TRST VS TDO TCK 1 2 3 4 5 6 7 8 9 IA IA IA IA OA OA 28 OUT1+ 27 OUT1– 26 IN1+ IA IA 25 IN1– 24 TEST 23 TEST Configuration Memory Analog Routing Pool Reference & Auto-Calibration 22 VREFOUT 21 GND 20 CAL IA IA 19 CMV IN 18 IN3– 17 IN3+ 16 OUT3– TMS 10 IN4– 11 IN4+ 12 OUT4– 13 OUT4+ 14 Description The ispPAC10 is a member of the Lattice family of InSystem Programmable analog circuits, digitally configured via nonvolatile E2CMOS technology. Analog function modules, called PACblocks™, replace traditional analog components such as op amps and active filters, eliminating the need for most external resistors and capacitors. With no requirement for external configuration components, ispPAC10 expedites the design process, simplifying prototype circuit implementation and change, while providing high performance and integrated functionality. Designers configure the ispPAC10 and verify its performance using PAC-Designer®, an easy-to-use, Microsoft Windows® compatible development tool. Device programming is supported using PC parallel port I/O operations. A library of configurations is included with basic solutions and examples of advanced circuit techniques. The ispPAC10 is configured through its IEEE Standard 1149.1 (JTAG) compliant serial port. The flexible InSystem Programming capability enables programming, verification and reconfiguration if desired, directly on the printed circuit board. OA OA 15 OUT3+ Typical Application Diagram 5V Vin 5V 12-Bit Differential Input ADC Ain+ Ain- Ref+ RefispPAC10 Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com September 2000 pac10_04 1 Specifications ispPAC10 TA = 25°C; VS = 5.0V; Signal path = VIN to VOUT of one PACblock (second input unused); 1V ≤ VOUT ≤ 4V; Gain = 1; Output load = 200pf, 1MΩ. Feedback enabled; Feedback capacitor = minimum; Auto-Cal initiated immediately prior. (Unless otherwise specified). DC Electrical Characteristics SYMBOL PARAMETER CONDITION Applied Either to VIN+ or VIN– 2| VIN+ – VIN– | G = 10 G=1 -40 to +85°C MIN. 1 6 TYP. MAX. UNITS 4 V Vp-p µV mV µV/°C Ω pF pA nV/√Hz V Vp-p mA V dB % % ppm/°C dB dB % V ppm/°C µA µA µVRMS dB cycles 0.8 VS ±10 +40/-70 0.5 V V µA µA V V V mA mW °C °C Analog Input VIN± (1) Input Voltage Range VIN-DIFF Differential Input Voltage Swing (2) VOS (2) Differential Offset Voltage (Input Referred) ∆VOS/∆T Differential Offset Voltage Drift RIN Input Resistance CIN Input Capacitance IB Input Bias Current eN Input Noise Voltage Density Analog Output VOUT± Output Voltage Range VOUT-DIFF Differential Output Voltage Swing (2) IOUT± Output Current VCM Common Mode Output Voltage Static Performance G Programmable Gain Range Gain Error Gain Matching ∆G/∆T Gain Drift PSR Power Supply Rejection Common Mode Reference Output (VREFOUT) VREFOUT Reference Output Voltage Range CMVIN (4) Common Mode Voltage Input Reference Output Voltage Drift IREFOUT Reference Output Current Reference Output Noise Voltage Reference Power Supply Rejection Programming Erase/Reprogram Cycles Digital I/O VIL VIH IIL, IIH Input Low Voltage Input High Voltage Input Leakage Current at DC At 10kHz, Referred to Input, G = 10 Present at Either VOUT+ or VOUT– 2| VOUT+ – VOUT– | Source/Sink (VOUT+ + VOUT-)/2 ; VIN+ = VIN– Each Individual PACblock RL = 300Ω Differential Between Two Inputs of Same PACblock -40 to +85°C Differential at 1kHz Single-ended at 1kHz Nominally 2.500V Optional External Common-Mode Voltage -40 to +85°C (VREFOUT = ±1%) Source (VREFOUT = ±1%) Sink 10MHz Bandwidth; 1µF Bypass Capacitor 1kHz 0.1 9.6 10 2.495 0 20 0.2 50 109 2 3 38 100 1.0 4.9 2.500 2.505 20 4.


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