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KM416C256D Dataheets PDF



Part Number KM416C256D
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description 256K x 16Bit CMOS Dynamic RAM with Fast Page Mode
Datasheet KM416C256D DatasheetKM416C256D Datasheet (PDF)

KM416C256D, KM416V256D 256K x 16Bit CMOS Dynamic RAM with Fast Page Mode DESCRIPTION CMOS DRAM This is a family of 262,144 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage (+5.0V or +3.3V), access time (-5,-6,-7), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refres.

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KM416C256D, KM416V256D 256K x 16Bit CMOS Dynamic RAM with Fast Page Mode DESCRIPTION CMOS DRAM This is a family of 262,144 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage (+5.0V or +3.3V), access time (-5,-6,-7), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 256Kx16 fast page mode DRAM family is fabricated using Samsung's advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines. ¡Ü Fast Page Mode operation 2 CAS Byte/Wrod Read/Write operation CAS-before-RAS refresh capability RAS-only and Hidden refresh capability Self-refresh capability (L-ver only) TTL(5V)/LVTTL(3.3V) compatible inputs and outputs Early Write or output enable controlled write JEDEC Standard pinout Available in 40-pin SOJ 400mil and44(40)-pin TSOP(II) 400mil packages Triple +5V¡¾10% power supply(5V product) Triple +3.3V¡¾0.3V power supply(3.3V product) FEATURES ¡Ü ¡Ü Part Identification - KM416C256D/DL (5V, 512K Ref.) - KM416V256D/DL (3.3V, 512K Ref.) ¡Ü ¡Ü ¡Ü ¡Ü ¡Ü Active Power Dissipation Unit : mW Speed -5 -6 -7 3.3V(512 Ref.) 325 290 5V(512 Ref.) 605 495 440 ¡Ü ¡Ü ¡Ü ¡Ü ¡Ü ¡Ü Refresh Cycles Part NO. C256D V256D VCC 5V 3.3V Refresh cycle 512K Refresh period Normal 8ms L-ver 128ms RAS UCAS LCAS W FUNCTIONAL BLOCK DIAGRAM Control Clocks Vcc Vss Lower Data in Buffer Sense Amps & I/O Lower Data out Buffer Upper Data in Buffer Upper Data out Buffer VBB Generator Refresh Timer ¡Ü Row Decoder Performance Range: Speed -5 -6 -7 DQ0 to DQ7 tRAC 50ns 60ns 70ns tCAC 15ns 15ns 20ns tRC 90ns 10ns 130ns tPC 35ns 40ns 45ns Remark 5V only 5V/3.3V 5V/3.3V A0 . . A8 Refresh Control Refresh Counter Row Address Buffer Col. Address Buffer Column Decoder Memory Array 262,144 x16 Cells OE DQ8 to DQ15 SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. KM416C256D, KM416V256D CMOS DRAM PIN CONFIGURATION (Top Views) ¡Ü KM416C/V256DJ ¡Ü KM416C/V256DT VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C N.C W RAS N.C A0 A1 A2 A3 VCC 1 ¡Û 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ¡Û 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C LCAS UCAS OE A8 A7 A6 A5 A4 VSS VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C N.C W RAS N.C A0 A1 A2 A3 VCC 1 ¡Û 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C LCAS UCAS OE A8 A7 A6 A5 A4 VSS ¡Û (SOJ) (TSOP-II) Pin Name A0 - A8 DQ0 - 15 VSS RAS UCAS LCAS W OE VCC N.C Pin Function Address Inputs Data In/Out Ground Row Address Strobe Upper Column Address Strobe Lower Column Address Strobe Read/Write Input Data Output Enable Power(+5V) Power(+3.3V) No Connection KM416C256D, KM416V256D ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol 3.3V VIN,VOUT VCC Tstg PD IOS -0.5 to +4.6 -0.5 to +4.6 -55 to +150 1 50 Rating CMOS DRAM Units 5V -1.0 to +7.0 -1.0 to +7.0 -55 to +150 1 50 V V ¡É W mA * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, T A= 0 to 70¡É) Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol Min VCC VSS VIH VIL 3.0 0 2.0 -0.3 *2 3.3V Typ 3.3 0 Max 3.6 0 VCC+0.3*1 0.8 Min 4.5 0 2.4 -1.0 *2 5V Typ 5.0 0 Max 5.5 0 VCC+1.0 *1 0.8 Units V V V V *1 : VCC+1.3V/15ns(3.3V), VCC+2.0V/20ns(5V), Pulse width is measured at VCC *2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at VSS DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Max Parameter Input Leakage Current (Any input 0¡ÂVIN¡ÂVIN+0.3V, all other input pins not under test=0 Volt) Output Leakage Current (Data out is disabled, 0V¡ÂVOUT¡ÂVCC) Output High Voltage Level(IOH=-2mA) Output Low Voltage Level(IOL=2mA) Input Leakage Current (Any input 0¡ÂVIN¡ÂVIN+0.5V, all other input pins not under test=0 Volt) Output Leakage Current (Data out is disabled, 0V¡ÂVOUT¡ÂVCC) Output High Voltage Level(IOH=-5mA) Output Low Voltage Level(IOL=4.2mA) Symbol II(L) Min -5 Max 5 Units uA 3.3V IO(L) VOH VOL II(L) -5 2.4 -5 5 0.4 5 uA V V uA 5V IO(L) VOH VOL -5 2.4.


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