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IDT74FCT533 Dataheets PDF



Part Number IDT74FCT533
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description FAST CMOS OCTAL TRANSPARENT LATCHES
Datasheet IDT74FCT533 DatasheetIDT74FCT533 Datasheet (PDF)

® FAST CMOS OCTAL TRANSPARENT LATCHES Integrated Device Technology, Inc. IDT54/74FCT373/A/C IDT54/74FCT533/A/C IDT54/74FCT573/A/C FEATURES • IDT54/74FCT373/533/573 equivalent to FAST™ speed and drive • IDT54/74FCT373A/533A/573A up to 30% faster than FAST • Equivalent to FAST output drive over full temperature and voltage supply extremes • IOL = 48mA (commercial) and 32mA (military) • CMOS power levels (1mW typ. static) • Octal transparent latch with 3-state output control • JEDEC standard pin.

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® FAST CMOS OCTAL TRANSPARENT LATCHES Integrated Device Technology, Inc. IDT54/74FCT373/A/C IDT54/74FCT533/A/C IDT54/74FCT573/A/C FEATURES • IDT54/74FCT373/533/573 equivalent to FAST™ speed and drive • IDT54/74FCT373A/533A/573A up to 30% faster than FAST • Equivalent to FAST output drive over full temperature and voltage supply extremes • IOL = 48mA (commercial) and 32mA (military) • CMOS power levels (1mW typ. static) • Octal transparent latch with 3-state output control • JEDEC standard pinout for DIP and LCC • Product available in Radiation Tolerant and Radiation Enhanced versions • Military product compliant to MIL-STD-883, Class B DESCRIPTION The IDT54/74FCT373/A/C, IDT54/74FCT533/A/C and IDT54/74FCT573/A/C are octal transparent latches built using an advanced dual metal CMOS technology. These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the set-up time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high-impedance state. FUNCTIONAL BLOCK DIAGRAMS IDT54/74FCT373 AND IDT54/74FCT573 D0 D O G G D1 D O G D2 D O G D3 D O G D4 D O G D5 D O G D6 D O G D7 D O LE OE O0 O1 O2 O3 O4 O5 O6 O7 2602 cnv* 01 IDT54/74FCT533 D0 D O G G D1 D O G D2 D O G D3 D O G D4 D O G D5 D O G D6 D O G D7 D O LE OE O0 O1 O2 O3 O4 O5 O6 O7 The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor Co. 2602 cnv* 02 MILITARY AND COMMERCIAL TEMPERATURE RANGES ©1992 Integrated Device Technology, Inc. MAY 1992 DSC-4624/2 7.12 1 IDT54/74FCT373/533/573/A/C FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS IDT54/74FCT373 OE 1 O0 D0 D1 O1 O2 D2 D3 O3 GND 2 3 4 5 6 7 8 9 10 19 18 P20-1 D20-1 16 SO20-2 15 & E20-1 14 13 12 11 17 O7 D7 D6 O6 O5 D5 D4 O4 LE D1 O1 O2 D2 D3 4 5 6 7 8 D0 3 O0 2 OE 1 20 VCC 20 19 18 17 16 15 14 VCC O7 INDEX D7 D6 O6 O5 D5 L20-2 9 10 11 12 13 O3 GND O4 1 DIP/SOIC/CERPACK TOP VIEW LCC TOP VIEW IDT54/74FCT573 D0 D1 D2 D3 D4 D5 D6 D7 GND 2 3 4 5 6 7 8 9 10 19 18 P20-1 D20-1 16 SO20-2 15 & 14 E20-1 13 12 11 17 O0 O1 O2 O3 O4 O5 O6 O7 LE 3 D2 D3 D4 D5 D6 4 5 6 7 8 9 10 11 12 13 L20-2 2 20 19 18 17 16 15 14 O1 O2 O3 O4 O5 D7 GND D1 OE LE OE 1 O7 DIP/SOIC/CERPACK TOP VIEW LCC TOP VIEW IDT54/74FCT533 D0 O0 D0 D1 O1 O2 D2 D3 O3 GND 2 3 4 5 6 7 8 9 10 19 18 P20-1 D20-1 16 SO20-2 15 & 14 E20-1 13 12 11 17 O7 D7 D6 O6 O5 D5 D4 O4 LE D1 O1 O2 D2 D3 4 5 6 7 8 9 10 11 12 13 L20-2 3 2 20 19 18 17 16 15 14 D7 D6 O6 O5 D5 O0 OE 1 20 VCC LE O3 GND O4 DIP/SOIC/CERPACK TOP VIEW LCC TOP VIEW 7.12 D4 VCC O7 INDEX O6 O0 D0 1 20 VCC OE VCC INDEX LE D4 2602 cnv* 03–08 2 IDT54/74FCT373/533/573/A/C FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES FUNCTION TABLE (FCT533)(1) DN H L X Inputs LE H H X Outputs FUNCTION TABLE (FCT373 and FCT573)(1) ON L H Z 2602 tbl 05 OE L L H DN H L X Inputs LE H H X OE L L H Outputs ON H L Z 2602 tbl 06 NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance PIN DESCRIPTION Pin Names DN LE Description Data Inputs Latch Enable Input (Active HIGH) Output Enable Input (Active LOW) 3-State Outputs Complementary 3-State Outputs 2602 tbl 07 OE ON ON ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Commercial VTERM(2) Terminal Voltage –0.5 to +7.0 with Respect to GND VTERM(3) Terminal Voltage –0.5 to VCC with Respect to GND TA Operating 0 to +70 Temperature TBIAS Temperature –55 to +125 Under Bias TSTG Storage –55 to +125 Temperature PT Power Dissipation 0.5 IOUT DC Output Current 120 Military –0.5 to +7.0 Unit V CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. 10 12 Unit pF pF –0.5 to VCC V –55 to +125 –65 to +135 –65 to +150 0.5 120 °C °C °C W mA NOTE: 2602 tbl 02 1. This parameter is measured at characterization but not tested. NOTES: 2602 tbl 01 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only. 7.12 3 IDT54/74FCT373/533/573/A/C FAST CMOS OCTAL TRANSPARENT LATCHES MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unl.


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