IDT70V657S

HIGH-SPEED 3.3V 32K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM Features True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 10/12/15ns (max.) – Industrial: 12/15ns (max.) Dual chip enables allow for depth expansion without external logic IDT70V657 easily expands data bus width to 72 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Busy and Interrupt Flags On-chip port arbitration logic x x x PRELIMINARY IDT70V657S x x x x x x x x x x x x Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port Separate byte controls for multiplexed bus and bus matching compatibility Supports JTAG features compliant to IEEE 1149.1 LVTTL-compatible, single 3.3V (±150mV) power supply for core LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV) power supply for I/Os and control signals on each port Available in 208-pin Plastic Quad Flatpack, 208-ball fine pitch Ball Grid Array and 256-ball Ball Grid Array Industrial temperature range (–40°C to +85°C) is available for selected speeds Functional Block Diagram BE 3L BE 2L BE3 R BE2 R BE 1R BE 0R R/WR B E 0 L B E 1 L B E 2 L B E 3 L B E 3 R BB EE 2 1 RR B E 0 R BE 1 L BE 0L R/W L CE0 L CE1 L CE 0 R CE1R OE L OE R Dout0-8_L Dout9-17_L Dout18-26_L Dout27-35_L Dout0-8_R Dout9-17_R Dout18-26_R Dout27-35_R 32...