IDT74FCT163501

3.3V CMOS 18-BIT REGISTERED TRANSCEIVER Integrated Device Technology, Inc. IDT74FCT163501/A/C FEATURES: 0.5 MICRON CMOS Technology Typical tSK(o) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP and 15.7 mil pitch TVSOP Extended commercial range of -40°C to +85°C VCC = 3.3V ±0.3V, Normal Range or VCC = 2.7 to 3.6V, Extended Range CMOS power levels (0.4µW typ. static) Rail-to-Rail output swing for increased noise margin Low Ground Bounce (0.3V typ.) Inputs (except I/O) can be driven by 3.3V or 5V components DESCRIPTION: The FCT163501/A/C 18-bit registered transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power 18-bit registered bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA) and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. OEAB performs the output enable function on the B port. Data flow from B port to A port is similiar but requires using OEBA, LEBA and CLKBA. Flow-th...