Document
Integrated Device Technology, Inc.
BUS-MATCHING BIDIRECTIONAL FIFO 512 x 18-BIT – 1024 x 9-BIT 1024 x 18-BIT – 2048 x 9-BIT
DESCRIPTION:
IDT72510 IDT72520
FEATURES:
• Two side-by-side FIFO memory arrays for bidirectional data transfers • 512 x 18-Bit – 1024 x 9-Bit (IDT72510) • 1024 x 18-Bit – 2048 x 9-Bit (IDT72520) • 18-bit data bus on Port A side and 9-bit data bus on Port B side • Can be configured for 18-to-9-bit, 36-to-9-bit, or 36-to-18bit communication • Fast 25ns access time • Fully programmable standard microprocessor interface • Built-in bypass path for direct data transfer between two ports • Two fixed flags, Empty and Full, for both the A-to-B and the B-to-A FIFO • Two programmable flags, Almost-Empty and Almost-Full for each FIFO • Programmable flag offset can be set to any depth in the FIFO • Any of the eight internal flags can be assigned to four external flag pins • Flexible reread/rewrite capabilities. • On-chip parity checking and generation • Standard DMA control pins for data exchange with peripherals • IDT72510 and IDT72520 available in the the 52-pin PLCC package
The IDT72510 and IDT72520 are highly integrated firstin, first-out memories that enhance processor-to-processor and processor-to-peripheral communications. IDT BiFIFOs integrate two side-by-side memory arrays for data transfers in two directions. The BiFIFOs have two ports, A and B, that both have standard microprocessor interfaces. All BiFIFO operations are controlled from the 18-bit wide Port A. The BiFIFOs incorporate bus matching logic to convert the 18-bit wide memory data paths to the 9-bit wide Port B data bus. The BiFIFOs have a bypass path that allows the device connected to Port A to pass messages directly to the Port B device. Ten registers are accessible through Port A, a Command Register, a Status Register, and eight Configuration Registers. The IDT BiFIFOs have programmable flags. Each FIFO memory array has four internal flags, Empty, Almost-Empty, Almost-Full and Full, for a total of eight internal flags. The Almost-Empty and Almost-Full flag offsets can be set to any depth through the Configuration Registers. These eight internal flags can be assigned to any of four external flag pins (FLGA-FLGD) through one Configuration Register. Port B has parity, reread/rewrite and DMA functions. Parity generation and checking can be done by the BiFIFO on data passing through Port B. The Reread and Rewrite con-
SIMPLIFIED BLOCK DIAGRAM
18-Bit FIFO
18-bits Data
Bypass Path
9-bits
9-bits Data
Port A
18-Bit FIFO
Port B
Registers Control Processor Interface A Processor Interface B Control
Flags
Programmable Flag Logic
Handshake Interface
DMA
The IDT logo is a registered trademark of Integrated Device Techology, Inc.
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©1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1995
DSC-2669/-
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1
IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
trols will read or write Port B data blocks multiple times. The BiFIFOs have three pins, REQ, ACK and CLK, to control DMA transfers from Port B devices.
PIN CONFIGURATION
LDREW LDRER GND GND DA16
DSA
VCC
DA9
DA8
INDEX
7 6 5 4 DA10 DA11 DA12 DA13 DA14 DA15 DA17 A0 A1 FLGD FLGC FLGB FLGA 8 9 10 11 12 13 14 15 16 17 18 19 20
3 2
RS
1
52 51 50 49 48 47 46 45 44 43 42 41 DA4 DA3 DA2 DA1 DA0
DA7 DA6 DA5
J52-1
40 39 38 37 36 35 34
CSA R/WA RER REW
REQ ACK CLK DB0
21 22 23 24 25 26 27 28 29 30 31 32 33
WB (R/WB )
RB (DSB)
DB8
DB7
DB6
DB5
DB4
DB3
DB2
GND
PLCC TOP VIEW
GND
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VCC
DB1
2
IDT72510, IDT72520 BUS MATCHING BIDIRECTIONAL FIFO
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol
DA0-DA15 DA16-DA17
Name
Data A Parity A
I/O
I/O I/O
Description
Data inputs and outputs for 16 bits of the 18-bit Port A bus. DA16 is the parity bit for DA0-DA7. DA17 is the parity bit for DA8DA15. DA16 and DA17 can be used as two extra data bits if the parity generate function is disabled. Port A is accessed when Chip Select A is LOW. Data is written into Port A on the rising edge of Data Strobe when Chip Select is LOW. Data is read out of Port A on the falling edge of Data Strobe when Chip Select is LOW. This pin controls the read or write direction of Port A. When CSA is LOW and R/WA is HIGH, data is read from Port A on the falling edge of DSA. When CSA is LOW and R/WA is LOW, data is written into Port A on the rising edge of DSA. When Chip Select A is asserted, A0, A1, and Read/Write A are used to select one of six internal resources. Data inputs and outputs for 8 bits of the 9-bit Port B bus. DB8 is the parity bit for DB0-DB7. DB8 can be used as a data bit if the parity generate function is disabled. If Port B is programmed to processor mode, this pin functions as an input. If Port B is programmed to peripheral mode this pin functions as an output. This pin can function as part of an Inte.